PLL Monitor Circuit Using Reference Signals for Clock Fault Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loop (PLL) circuits in System-on-Chip (SoC) circuits face issues such as incorrect frequency, duty cycle, stuck or floating output signals, loss of lock, missing or extra pulses, and excessive jitter noise, which can impact overall SoC performance.
Innovation Solution
A PLL architecture that includes a reference PLL circuit, a main PLL circuit, and a PLL monitor circuit, which dynamically detects issues by using reference signals to ensure the main PLL output signal is correct and reliable, incorporating monitors for minimum pulse violation, lock time, loss of lock, and frequency anomalies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL circuit is used for clock signal distribution in high performance systems, then phase/delay compensation and frequency multiplication are achieved, but the system becomes vulnerable to issues such as incorrect frequency, duty cycle errors, loss of lock, and excessive jitter noise
Solution Approach 1:
The patent implements preliminary monitoring actions by continuously checking PLL output signals for anomalies before they can cause system failures. The monitor circuit proactively detects issues such as incorrect frequency, duty cycle errors, and loss of lock conditions, allowing the system to take corrective action before these issues impact overall system performance.
Solution Approach 2:
The patent employs feedback mechanisms where the monitor circuit continuously observes PLL output signals and feeds back anomaly detection information to control logic. This feedback loop enables real-time detection and response to issues such as frequency errors, phase anomalies, and lock loss conditions, allowing the system to maintain reliability through continuous monitoring and corrective action.
2Reliability
If a PLL monitor circuit is added to detect issues in real-time, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the monitoring function into distinct modular components, including separate monitor circuits for different PLL outputs and specialized anomaly detection units. This segmentation allows the monitoring system to be built from independent, manageable modules, reducing overall complexity while maintaining comprehensive monitoring coverage.
Solution Approach 2:
The patent implements universal monitor circuits that can detect multiple types of anomalies (frequency errors, phase anomalies, duty cycle errors, lock loss) using a single integrated monitoring structure. This multi-functional approach reduces device complexity by eliminating the need for separate dedicated circuits for each anomaly type, while still providing comprehensive monitoring coverage.
Data Source
AI summary
A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.