PLL Reference Frequency Doubling for Delta-Sigma Noise Reduction
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Solution Overview
Problem
Fractional phase locked loops with low reference signal frequencies struggle to filter noise from delta-sigma modulation, leading to noise contamination in output signals, particularly in Bluetooth Low Energy standards where the reference signal is 16 MHz and the output signal is 2.4 GHz, and existing solutions like dual phase comparators introduce excessive phase noise.
Innovation Solution
A method and device that doubles the reference frequency of a phase locked loop using a single phase comparator, generating a secondary reference signal with synchronized edges, reducing phase noise contributions and utilizing the output signal of the voltage-controlled oscillator to create a pulse for effective phase comparator operation, with a duty cycle optimized for efficient noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the reference signal frequency is kept low (e.g., 16 MHz), then the phase locked loop can operate with simpler components, but the loop cannot properly filter the noise resulting from delta-sigma modulation
Solution Approach 1:
The patent changes the frequency parameter of the reference signal from 16 MHz to 32 MHz (doubling it). This parameter change enables the phase locked loop to properly filter delta-sigma modulation noise while maintaining the same hardware architecture, thus resolving the contradiction between device complexity and noise filtering capability.
2Speed
If a dual phase comparator architecture is used to double the reference frequency, then the reference frequency can be doubled (e.g., to 32 MHz), but many contributions to phase noise are introduced
Solution Approach 1:
The patent merges the frequency doubling function into a single phase comparator by using its dual-edge detection capability. Instead of using two separate phase comparators as in conventional solutions, the invention combines both rising and falling edge detections in one component, thereby achieving frequency doubling while minimizing phase noise contributions.
Solution Approach 2:
The patent makes the single phase comparator perform multiple functions: it detects both rising and falling edges of the reference signal, effectively doubling the frequency while maintaining low phase noise. This multi-functionality eliminates the need for separate components and reduces overall phase noise contributions.
3Speed
If a dual phase comparator architecture is used to double the reference frequency, then the frequency can be doubled, but the signal is not usable by other devices in the integrated circuit
Solution Approach 1:
The patent introduces a signal generation circuit as an intermediary that takes the 32 MHz doubled frequency signal from the phase comparator and generates additional signals at the same frequency for use by other devices in the integrated circuit. This intermediary ensures that the high-frequency signal remains usable across multiple components while maintaining the benefits of frequency doubling.
Data Source
AI summary
In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.