PLL Reference Loss Detection Using Feedback Code Comparison
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Solution Overview
Problem
Existing phase lock loop (PLL) circuits in electronic systems fail to promptly detect the loss of an input reference signal, leading to potential system malfunctions and data loss due to delayed detection and increased electrical noise, circuit costs, and complexity in clock domain reconciliation.
Innovation Solution
A code-based loss detector system using a pseudo-random number generator to generate unique codes each clock cycle, which are serially shifted through registers, comparing values to detect input reference signal loss, and a backup clock generator to mitigate potential failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock generator is used for ratiometric comparison to detect reference signal loss, then detection capability is improved, but circuit costs, power dissipation, and noise increase
Solution Approach 1:
The patent makes the existing feedback clock serve multiple functions: it continues to provide phase synchronization for the PLL while simultaneously enabling reference signal loss detection through code generation and comparison. This eliminates the need for a separate dedicated detection clock generator, reducing circuit complexity and power consumption while maintaining detection capability.
Solution Approach 2:
The patent combines the reference signal loss detection function with the existing PLL feedback mechanism. By generating codes based on the feedback clock and comparing them with expected values, the system merges detection functionality into the existing clock generation pathway, avoiding additional separate clock domains and reducing overall system complexity.
2Reliability
If ratiometric determination with a threshold is used for detection, then false positives are reduced, but detection delay increases
Solution Approach 1:
The patent generates and compares codes continuously in advance using the feedback clock, so that when a reference signal loss occurs, the comparison can immediately detect the anomaly without waiting for accumulated cycle counts. This preliminary continuous code generation eliminates detection delay while maintaining accuracy through the threshold-based comparison mechanism.
3Measurement precision
If counters are clocked by a high-frequency local reference clock, then counting precision is improved, but power dissipation and noise increase
Solution Approach 1:
The patent uses short code sequences generated from the feedback clock that are continuously compared and discarded, rather than maintaining continuous high-frequency counting operations. This approach achieves sufficient detection precision through brief code comparisons while avoiding the sustained power consumption and noise associated with continuously clocking high-frequency counters.
Data Source
AI summary
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.