PLL Reference Loss Detection Using Code-Based Clock Monitoring
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Solution Overview
Problem
Existing PLL clock generation systems fail to promptly detect the loss of an input reference signal, leading to system malfunctions and data loss due to delayed detection and increased noise from ratiometric comparisons and separate clock domains, which can result in false-positive indications and circuit inefficiencies.
Innovation Solution
A code-based loss detector circuit that generates unique codes each clock cycle using a pseudo-random number generator, with a PLL-derived clock shifting codes through serial registers, allowing for early detection of input reference signal loss by comparing register values, thereby mitigating potential damage with reduced noise and false positives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ratiometric comparison is used for reference signal loss detection, then detection capability is provided, but detection delay increases and noise is generated
Solution Approach 1:
The patent extracts the detection function from the main PLL circuit by implementing a separate loss detector that independently monitors the reference signal. This detector uses a code generator and serial register comparison mechanism that operates independently of the ratiometric comparison process, thereby eliminating detection delays associated with the main clock generation path while providing prompt loss detection.
Solution Approach 2:
The patent introduces an intermediary code generator that creates unique codes for each reference clock cycle. These codes serve as intermediaries to detect reference signal loss by comparing sequential code values in serial registers, providing a noise-free detection mechanism that does not rely on ratiometric comparisons and enables immediate detection without delay.
2Reliability
If separate clock domains are used for detection, then detection function is provided, but noise and false positives increase
Solution Approach 1:
The patent merges the detection function with the existing PLL clock domain by using the same reference clock to drive both the code generator and the PLL. This eliminates the need for separate clock domains, thereby avoiding the noise and false positives that arise from clock domain crossings and synchronization issues while maintaining effective loss detection capability.
3Reliability
If prompt detection is implemented, then system integrity is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the detection function into distinct modular components: a code generator that produces unique codes, serial registers that store and shift codes, and a comparison mechanism that detects losses. This segmentation provides prompt detection for system integrity while keeping each component simple and manageable, avoiding excessive overall circuit complexity.
Solution Approach 2:
The patent uses a simple code generation approach where unique codes are created for each reference clock cycle and copied into serial registers. The loss detection is achieved by comparing these copied code values, providing a low-complexity mechanism that enables prompt detection and maintains system integrity without requiring complex circuitry.
Data Source
AI summary
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.