PLL Reference Switching With Divider-Aware Phase Alignment
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges when switching between reference clock signals due to arbitrary phase offsets introduced by input dividers, which can lead to undesired phase movements and restrict the frequency of inputs, especially in systems using time-to-digital conversion.
Innovation Solution
The implementation of a method that involves dividing both reference clock signals and using time-to-digital converters to align the PLL output with the nearest edge of the input reference signal, performing a phase adjustment corresponding to an integral number of clock periods to remove the phase difference, thereby ensuring the phase offset seen by the PLL is consistent with the intended phase offset between the input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If input dividers are used to divide reference clock signals before use in the PLL, then the PLL can operate at lower frequencies and have extended frequency range, but arbitrary phase offsets are introduced that cause undesired phase movements when switching between reference signals
Solution Approach 1:
The patent calculates the phase offset between divided reference signals in advance using the formula: phase_offset = (divider2_value - divider1_value) × reference_clock_period. This preliminary calculation allows the system to pre-determine the correct phase adjustment value before switching occurs, eliminating arbitrary phase movements and ensuring stable phase relationships when switching between reference signals.
Solution Approach 2:
The patent dynamically adjusts the phase adjustment parameter based on the values of the input dividers. By changing the phase adjustment parameter according to the formula above, the system compensates for the phase offsets introduced by different divider configurations, allowing the PLL to maintain phase stability across different frequency operating points and when switching between reference signals.
2Stability of the object's composition
If input dividers are bypassed to avoid phase offset issues, then phase stability is maintained, but the frequency flexibility and ability to use time-to-digital conversion are restricted
Solution Approach 1:
The patent introduces a phase adjustment mechanism as an intermediary between the input dividers and the PLL core. This mediator calculates and applies the appropriate phase offset compensation based on the divider values, allowing the system to use input dividers for frequency flexibility while maintaining phase stability. The phase adjustment acts as a bridge that reconciles the conflicting requirements of using dividers for frequency range extension while avoiding their harmful phase offset effects.
3Adaptability or versatility
If the PLL switches between different reference clock signals, then signal selection flexibility is improved, but arbitrary phase offsets cause the PLL output to move by undesired amounts
Solution Approach 1:
Before switching between reference clock signals, the system pre-calculates the phase offset that will result from the divider configuration using the formula: phase_offset = (divider2_value - divider1_value) × reference_clock_period. This preliminary calculation ensures that when the switch occurs, the phase adjustment is already determined, preventing arbitrary phase movements and maintaining precise phase alignment during signal selection transitions.
Solution Approach 2:
The system uses feedback from the divider values to dynamically adjust the phase compensation. By monitoring the divider configurations and using them to calculate the required phase adjustment, the system creates a closed-loop control mechanism that ensures precise phase alignment is maintained during reference signal switching, eliminating the arbitrary phase offsets that would otherwise occur.
Data Source
AI summary
A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.