Multi-Loop PLL Reference Switching for Fast Lock and Fine Tuning
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Solution Overview
Problem
Existing phase locked loop (PLL) circuits are limited in convergence speed, making them inadequate for high-frequency applications such as Ultra Wideband (UWB) systems, which require faster locking times.
Innovation Solution
A multi-loop PLL apparatus comprising two loops with different frequency reference signals, where the PLL initially locks using a high-frequency reference clock and then switches to a lower frequency signal for gradual locking, utilizing a control circuit to manage the transition and a loop filter to generate control signals for the voltage-controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-loop PLL with low-frequency reference clock is used, then the system achieves stable locking, but the locking time is excessively long
Solution Approach 1:
The PLL system is divided into two separate loops: a first loop with a first reference clock signal and a second loop with a second reference clock signal. The control circuit selectively activates either the first loop or the second loop based on locking requirements, enabling the system to segment the locking process into rapid initial acquisition (using second loop) and stable fine-tuning (using first loop).
Solution Approach 2:
The system dynamically switches between different reference clock frequencies based on the locking state. The control circuit monitors the locking process and transitions from using the high-frequency second reference clock for rapid locking to the low-frequency first reference clock for stable operation, making the system adaptable to different operational phases.
2Loss of time
If a high-frequency reference clock is used for rapid locking, then the locking time is reduced, but the system cannot achieve stable fine-tuning
Solution Approach 1:
The locking process is segmented into two phases: rapid acquisition phase using the second loop with high-frequency reference clock, and stable fine-tuning phase using the first loop with low-frequency reference clock. This segmentation allows each loop to be optimized for its specific function.
Solution Approach 2:
The second loop with high-frequency reference clock performs preliminary locking action to quickly bring the VCO frequency close to the target frequency. After this preliminary action, the first loop takes over for precise fine-tuning, ensuring both rapid response and stable operation.
Data Source
AI summary
Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.