Wireless Transceiver Reference Clock Switching for Mixer Phase Noise
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Solution Overview
Problem
Electronic devices with wireless communications circuitry face issues with excessive phase noise in clock signals, which can degrade transmission and reception quality, particularly in high-frequency applications where phase noise from mixers can accumulate and interfere with signal integrity.
Innovation Solution
The implementation of a transceiver with switchable clocking circuitry that uses high side injection (HSI) or low side injection (LSI) modes, featuring a reference oscillator, phase-locked loops (PLLs), and a switch to correlate or decorrelate clock signals, thereby minimizing phase noise injection by correlating or reducing the correlation between the clock signals used by the mixers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If mixers are used to convert signals between baseband and radio frequencies, then frequency conversion capability is improved, but phase noise is injected into the signal which degrades transmission and reception quality
Solution Approach 1:
The patent combines multiple mixers (first mixer for baseband to intermediate frequency conversion, second mixer for intermediate to radio frequency conversion) into a cascaded frequency conversion system. By merging these conversion stages and correlating their clock signals through shared PLL circuitry, the system achieves high frequency conversion capability while the correlated phase noise from both mixers cancels out, resolving the contradiction between conversion capability and phase noise injection.
Solution Approach 2:
The patent converts the harmful phase noise injected by mixers into a beneficial effect by deliberately correlating the clock signals of multiple mixers. The phase noise, which would normally be harmful, becomes useful because identical phase noise from correlated clock signals cancels out during the frequency conversion process, transforming the harmful factor into a mechanism that improves signal quality.
2Adaptability or versatility
If high side injection mode is used for frequency conversion, then certain frequency ranges are achieved, but phase noise correlation increases which may be detrimental in low side injection scenarios
Solution Approach 1:
The patent implements dynamic adaptability by making the clocking circuitry switchable between high side injection and low side injection modes, and by dynamically selecting between different reference clock sources (reference oscillator or reference PLL output) based on the current injection mode. This dynamic configuration allows the system to adapt to different frequency conversion scenarios while managing phase noise correlation appropriately for each mode.
Solution Approach 2:
The patent changes the correlation parameter of clock signals dynamically based on the injection mode. In high side injection mode, clock signals are correlated to achieve phase noise cancellation, while in low side injection mode, the system can decorrelate the clock signals by selecting different reference sources, thereby adapting the phase noise characteristics to match the operational requirements of each injection mode.
3Object-generated harmful factors
If multiple PLLs are used to generate correlated clock signals for mixers, then phase noise cancellation is improved, but device complexity increases
Solution Approach 1:
The patent makes the PLL circuitry multi-functional by designing it to serve multiple purposes: generating correlated clock signals for phase noise cancellation, providing switchable reference sources, and supporting both high side and low side injection modes. The same PLL infrastructure is used universally across different operational modes, reducing the need for separate dedicated circuits for each function and thereby managing complexity while maintaining phase noise cancellation capabilities.
4Reliability
If clock signals are correlated to cancel phase noise, then signal integrity is improved, but adaptability to different injection modes is reduced
Solution Approach 1:
The patent implements dynamic switching capability that allows the system to change clock signal correlation characteristics based on the operational mode. The clocking circuitry can dynamically correlate clock signals when operating in high side injection mode to improve signal integrity through phase noise cancellation, and dynamically decorrelate them when operating in low side injection mode to maintain adaptability, thereby resolving the contradiction between reliability and versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces phase noise across both HSI and LSI modes, enhancing the signal integrity and performance of wireless communications by dynamically adjusting clock signal correlations to minimize overall phase noise, thereby improving transmission and reception quality.
Implementation Method 1
The reference PLL may generate a second reference signal by upconverting the first reference signal
Implementation Method 2
The radio frequency PLL may generate the second clock signal by upconverting the second reference signal
Implementation Method 3
The first mixer may convert a signal on the signal path between a baseband frequency and an intermediate frequency using a first clock signal. The second mixer may convert the signal between the intermediate frequency and a radio frequency using a second clock signal
Data Source
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AI summary
An electronic device (10) may include wireless circuitry (24) with first and second mixers (38, 40) on a signal path (36) for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch (72) may couple the first PLL to a reference oscillator (66) when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator (66). The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers (38, 40) switch between HSI and LSI.