PLL Timing Alignment Using Replica Delay for Multi-Chip Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation systems face challenges in aligning multiple clock signals to a common reference signal due to phase uncertainties caused by temperature and manufacturing process variations, leading to misalignment of input and output phases in phase-locked loops (PLLs).
Innovation Solution
A timing alignment circuit is introduced that replicates the path delay of the reference signal path within the PLL, adjusting the phase of the feedback signal to align the output rising edge with the input rising edge by adding a predetermined amount of delay, thereby phase-locking the input and output phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a PLL circuit is used to generate clock signals, then frequency multiplication and signal generation are achieved, but phase misalignment occurs between input and output signals due to path delay differences
Solution Approach 1:
The patent applies preliminary action by adding a timing alignment circuit that replicates the reference signal path delay before the PLL processing. This pre-compensation delay is calculated based on the known path delay characteristics, allowing the feedback signal to be advanced in phase to counteract the expected delay through the PLL, thereby achieving precise input-output phase alignment
Solution Approach 2:
The patent uses copying by creating a replica of the reference signal path delay characteristics in the timing alignment circuit. This replica delay circuit is designed to match the delay properties of the actual reference path, allowing accurate phase compensation to be applied to the feedback signal without requiring direct measurement of the actual path delays
2Manufacturing precision
If delay compensation is added to align phases, then phase alignment accuracy improves, but system complexity increases due to additional timing alignment circuitry
Solution Approach 1:
The timing alignment circuit is designed to be universally applicable to different PLL configurations by parameterizing the delay compensation based on measured or calculated path delays. The same circuit topology can be used across multiple designs by adjusting the delay values to match the specific reference path characteristics, reducing design complexity while maintaining high phase alignment accuracy
3Reliability
If path delay variations due to temperature and manufacturing processes are considered, then phase alignment robustness improves, but design and calibration complexity increases
Solution Approach 1:
The patent applies dynamics by making the delay compensation values adjustable and adaptable to environmental conditions. The timing alignment circuit can be calibrated during manufacturing to account for process variations, and some embodiments allow for temperature compensation by adjusting delay values based on operating conditions, thereby maintaining robust phase alignment across different environments without requiring overly complex real-time control mechanisms
Data Source
AI summary
The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.