Phase-Locked Loop Reset Scheme to Prevent VCO Harmonic Lock

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Solution Overview

Problem

Phase locked loops (PLLs) face limitations in generating high-speed clock signals due to harmonic lock issues when increasing the number of delay cells in the voltage controlled oscillator (VCO), which can prevent proper functioning.

Innovation Solution

Incorporating a harmonic lock detector to generate a reset signal and reset remaining delay cells in the VCO, excluding the first delay cell, to prevent harmonic lock and maintain operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the number of delay cells in the VCO is increased to generate high-speed clock signals, then the clock signal frequency is improved, but harmonic lock occurs which prevents proper PLL functioning

Engineering Contradiction:

Improveclock signal frequencyVSAvoidPLL proper functioning

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The VCO is divided into multiple delay cells (first delay cell and remaining delay cells) that can be independently controlled. The reset switch selectively resets only the remaining delay cells while the first delay cell continues operating, segmenting the reset function to prevent harmonic lock while maintaining high-speed clock generation capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the operational state of delay cells by introducing a reset signal that modifies the bias current or initialization state of the remaining delay cells. This parameter change allows the PLL to escape from harmonic lock condition while maintaining the high-frequency operation enabled by multiple delay cells

Inventive Principle:

Principle #35Parameter changes

2Speed

If the number of delay cells is increased to overcome frequency limits, then the clock signal speed is improved, but harmonic lock occurs

Engineering Contradiction:

Improveclock signal speedVSAvoidharmonic lock

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The reset switch is configured to preemptively or reactively reset the remaining delay cells when harmonic lock is detected, applying a counter-action that prevents the harmonic lock from persisting. This preliminary anti-action eliminates the harmful harmonic lock effect while preserving the high-speed clock signal generation

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The invention converts the harmful harmonic lock condition into a useful reset trigger. By detecting harmonic lock and using it to activate the reset switch, the system transforms the harmful effect into a beneficial self-correcting mechanism that maintains reliable operation of the high-speed clock generator

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS9525545B2Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same

Publication Date: 2016.12.20 SAMSUNG ELECTRONICS CO LTD

AI summary

A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.