PLL Reset Control Circuit for Faster Stable Initialization
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Solution Overview
Problem
Functional circuits, such as phase locked loop circuits, require excessive setting time to stabilize due to unstable output voltage during initialization, primarily because the negative feedback mechanism has not yet stabilized, leading to inefficiencies.
Innovation Solution
A control circuit comprising a reset circuit and a determination circuit that performs a reset operation on a digital circuit and determines whether a predetermined time interval has elapsed to stop the reset operation, ensuring the analog circuit has stabilized before discontinuing the reset, thereby optimizing the setting time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the functional circuit is initialized without reset control, then the circuit can start operating, but the output voltage remains unstable during time interval T11 because the negative feedback mechanism has not yet stabilized
Solution Approach 1:
The reset circuit performs a preliminary reset action on the digital frequency divider before the phase-locked loop stabilizes. This preliminary action clears any unstable states in the digital circuit before the analog feedback mechanism settles, allowing the system to transition more quickly from unstable to stable operation without sacrificing reliability.
Solution Approach 2:
The reset circuit acts as an intermediary between the power-on event and the phase-locked loop operation. It mediates the transition by temporarily holding the digital frequency divider in a reset state during the critical stabilization period T11, preventing the digital circuit from operating with unstable analog inputs while still enabling quick startup.
2Reliability
If continuous reset operation is performed to ensure digital circuit stability, then the digital circuit remains stable, but the setting time increases by at least time interval T12 after the analog circuit has stabilized
Solution Approach 1:
The reset operation is made dynamic rather than static. The determination circuit continuously monitors the stability status of the phase-locked loop and dynamically adjusts the reset signal duration. The reset operation starts immediately upon power-on and automatically stops when stability is detected, adapting the reset duration to actual circuit conditions rather than using a fixed time interval.
Solution Approach 2:
A feedback mechanism is introduced where the determination circuit monitors the output voltage stability and feeds this information back to control the reset circuit. When the feedback indicates that the phase-locked loop has stabilized (after time T11), the reset circuit stops its operation, thereby eliminating the unnecessary extended reset period T12 and reducing total setting time while maintaining digital circuit stability.
Data Source
AI summary
A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.