PLL Loop Filter Without Resistor Noise for Low Phase Noise
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Solution Overview
Problem
Existing phase lock loop (PLL) circuits face challenges in achieving low noise operating characteristics due to resistor noise in the loop filter circuit, which degrades overall phase noise and requires significant circuit area for capacitors.
Innovation Solution
The proposed PLL circuit design eliminates resistor noise by using a loop filter with only a capacitor, and introduces a second charge pump circuit to split integral and proportional control, allowing for increased charge pump current and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional loop filter with resistor and capacitor is used, then the PLL circuit can achieve stable frequency control, but resistor noise degrades the phase noise performance
Solution Approach 1:
The patent removes the resistor component from the loop filter circuit, extracting the noise-generating element while preserving the frequency control function through alternative means (charge pump circuitry and capacitor-only filtering). This directly eliminates resistor noise from the system.
Solution Approach 2:
The patent replaces the traditional voltage-mode loop filter with a current-mode filtering approach using charge pump circuitry. The charge pump converts phase error signals into current pulses that are integrated by a capacitor, substituting the resistor-capacitor voltage filtering mechanism with a current-integration approach that avoids resistor noise.
2Reliability
If the capacitor size is increased to reduce phase noise, then the phase noise performance improves, but the circuit area increases significantly
Solution Approach 1:
The patent replaces the passive RC filtering mechanism with an active charge pump-based current integration approach. This substitution allows for much smaller capacitor values because the charge pump actively maintains the control voltage through controlled current charging, rather than relying on large capacitors for passive noise filtering.
Solution Approach 2:
The patent changes the operating parameters of the loop filter from voltage-mode with large capacitance to current-mode with small capacitance. By using the charge pump to generate precise current pulses that integrate onto a small capacitor, the system achieves the same or better noise performance with dramatically reduced capacitor area.
3Speed
If the charge pump current is increased to improve loop response, then the locking speed improves, but the circuit power consumption increases
Solution Approach 1:
The patent implements dynamic charge pump current control where the current magnitude adjusts based on the phase error magnitude. During acquisition, larger current pulses provide fast locking. During steady-state operation, smaller currents maintain frequency while consuming less power. This dynamic adaptation resolves the speed-power tradeoff.
Solution Approach 2:
The charge pump operates in periodic bursts synchronized with the phase detection events rather than continuously. Current is pumped only when phase correction is needed, providing fast response when required while minimizing power consumption during steady-state operation when phase error is minimal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved low noise operation without increasing the KVCO gain or capacitor area, enabling better phase noise performance and increased charge pump current for enhanced circuit efficiency.
Implementation Method 1
a loop filter comprising a capacitor but no resistor that filters the first charge pump signal to generate a control voltage
Data Source
AI summary
A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.