Fractional Analog PLL Re-Timing for Divider-Free Low-Power Lock
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Solution Overview
Problem
Phase lock loops (PLLs) in wireless devices consume significant power, especially in sleep or listen modes, due to the power consumption of the feedback divider circuit, which limits battery life and performance in high-frequency wireless communications.
Innovation Solution
An integrated circuit with a fractional PLL configured to run in a divider disabled mode, using a re-timed clock signal and sigma-delta modulation to adjust the VCO output without the feedback divider, reducing power consumption and improving residual frequency error and phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the feedback divider circuit is enabled in a fractional PLL, then accurate frequency locking is achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the feedback divider circuit from the PLL system during low-power modes, separating the frequency locking function from the power-consuming divider. The VCO operates independently without the feedback divider, achieving acceptable frequency accuracy while eliminating the divider's power consumption. This extraction allows the system to maintain essential PLL functionality without the harmful power-draining component.
2Duration of action of moving object
If the feedback divider circuit is disabled to reduce power consumption, then battery life is extended, but frequency locking accuracy deteriorates
Solution Approach 1:
The patent implements dynamic operation of the feedback divider circuit, switching it between enabled and disabled states based on operational mode. During high-power modes, the divider is enabled for accurate frequency locking. During low-power sleep or listen modes, the divider is disabled to conserve battery life. This dynamic adaptation allows the system to optimize the trade-off between frequency accuracy and power consumption according to real-time requirements.
3Use of energy by moving object
If the VCO runs in open-loop mode without feedback divider, then power consumption is reduced, but residual frequency error and phase noise increase
Solution Approach 1:
The patent applies partial feedback by using a simplified error detection mechanism that compares the VCO output frequency with the reference frequency without requiring the full feedback divider circuit. This partial feedback action is sufficient to reduce residual frequency error and phase noise to acceptable levels while maintaining the power savings from operating without the complete feedback divider. The system performs just enough feedback to achieve adequate performance without the full power cost.
Data Source
AI summary
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.