Fractional-N PLL Retuning for Phase Interpolator Jitter Control
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Solution Overview
Problem
Phase interpolators in data transceiver architectures suffer from periodic jitter due to non-ideal performance, which affects link quality and requires regulation to meet modern high-speed serial communications standards.
Innovation Solution
The method involves using a fractional-N phase-locked loop (PLL) to receive a reference clock, measuring the parts per million (PPM) offset between incoming data and the reference clock, and tuning the center frequency to restrict jitter to specific frequencies within a predefined bandwidth, thereby reducing the PPM offset and shifting spurious periodic jitter to harmless locations in the frequency spectrum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If phase interpolators are used to offset transmit frequency relative to local timing reference, then frequency matching between transmit and receive can be achieved, but periodic jitter is introduced that degrades link quality
Solution Approach 1:
The patent measures the periodic jitter introduced by the phase interpolator and deliberately retunes the PLL to the same offset frequency, converting the harmful jitter into a predictable, measurable, and compensatable effect. By measuring the jitter spectrum and identifying its dominant frequency, the system can then apply corrective phase adjustments at that specific frequency to cancel out the periodic jitter's impact on link quality
Solution Approach 2:
The patent implements a feedback mechanism where the periodic jitter is measured using a jitter measurement circuit, and this measurement is used to control the PLL retuning process. The system continuously monitors the jitter introduced by the phase interpolator and adjusts the PLL frequency accordingly, creating a closed-loop control system that adaptively compensates for the periodic jitter while maintaining frequency matching capability
2Reliability
If PLL is retuned to compensate for periodic jitter, then link quality improves, but frequency offset from desired transmit frequency occurs
Solution Approach 1:
The patent applies partial correction by retuning the PLL to compensate for only the dominant periodic jitter component rather than attempting to eliminate all frequency offsets. By identifying and compensating for the primary jitter frequency through spectral analysis, the system achieves sufficient link quality improvement without over-correcting to the point of creating new frequency accuracy problems
Solution Approach 2:
The patent dynamically changes the PLL tuning parameters based on measured jitter characteristics. The system adjusts the PLL frequency offset parameter in response to measured periodic jitter, allowing the frequency to vary adaptively rather than remaining fixed, thereby optimizing link quality while managing frequency accuracy through controlled parameter variation
Data Source
AI summary
In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.