Ring Oscillator Realignment Circuit for PVT-Stable PLL Timing
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Solution Overview
Problem
Current ring oscillators in phase-locked loop (PLL) circuits face challenges in reducing phase noise and frequency variations due to process, voltage, and temperature (PVT) variations, which affect their performance across different applications.
Innovation Solution
The implementation of a ring oscillator with a controlling circuit and a delay chain that includes pseudo pass-gate inverters and dummy transistors, where a realignment signal is used to enable or disable the pseudo pass-gate inverter, allowing for phase alignment without additional electronic components, thereby reducing phase noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional ring oscillators are used in PLL circuits, then the circuit can generate clock signals across a wide frequency range, but the phase noise and frequency variations increase due to PVT variations
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the phase of individual oscillator signals using controllable delay elements before they are combined in the ring oscillator. This pre-adjustment compensates for expected PVT variations, allowing the oscillator to maintain stable frequency and reduced phase noise across wide frequency ranges and environmental conditions.
2Reliability
If additional electronic components are added to reduce phase noise and align phase, then the phase stability improves, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs universal components that serve multiple functions: the same controllable delay elements are used both for phase adjustment and for frequency tuning across different operating conditions. This multi-functionality reduces the need for separate dedicated phase-correction components, thereby maintaining phase stability without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the phase alignment function with the existing oscillator structure by integrating controllable delay elements directly into the oscillator circuit path. This consolidation allows phase correction to be achieved using the same component framework already present for frequency generation, reducing overall component count and simplifying the circuit architecture.
3Adaptability or versatility
If the ring oscillator operates across wide frequency ranges to cover PVT variations, then the adaptability improves, but the phase noise increases
Solution Approach 1:
The patent implements feedback mechanisms where the phases of individual oscillator signals are continuously monitored and adjusted using controllable delay elements. This feedback loop compensates for phase noise generated during wide frequency range operation, allowing the system to maintain low phase noise across the entire frequency spectrum by dynamically correcting deviations as they occur.
Data Source
AI summary
A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.