PLL Phase Detection Using SAR-ADC for Lower Power Operation
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Solution Overview
Problem
Existing all-digital phase-locked loops (ADPLLs) face challenges in reducing power consumption, particularly due to the high power consumption of time-to-digital converter (TDC) circuits when detecting large phase differences between reference and DCO frequencies, which limits intermittent operation and power reduction.
Innovation Solution
The implementation of a phase-locked loop with a SAR-ADC that uses two capacitors and a current source, where a first switch operates between one capacitor and the current source with a reference frequency clock and a second switch operates between another capacitor and the current source with a higher frequency clock, allowing for efficient voltage comparison and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TDC circuit uses a large number of inverter circuits to generate delay for detecting large phase differences, then the phase difference detection capability is improved, but the current consumption increases
Solution Approach 1:
The patent replaces the mechanical/digital inverter-based delay generation system with an analog voltage-based delay representation system. Instead of using multiple inverter stages to create time delays, the invention uses voltage levels to represent delay amounts, which are then processed by a SAR-ADC converter. This substitution dramatically reduces power consumption while maintaining the ability to represent and detect phase differences.
Solution Approach 2:
The patent changes the parameter representation from time-domain (actual time delays through inverter stages) to voltage-domain (voltage levels proportional to delay amounts). By using voltage levels to encode delay information and processing it through a SAR-ADC, the system achieves the same functional capability with significantly lower power consumption.
2Measurement precision
If the charge pump operates for several clock periods to obtain voltages for large phase differences, then the phase difference measurement accuracy is improved, but the intermittent operation rate decreases
Solution Approach 1:
The patent performs preliminary action by pre-charging capacitors to voltages proportional to the delay amounts before the actual phase difference measurement is needed. The delay line generates voltage representations of possible delay amounts in advance, and the SAR-ADC converts these to digital values beforehand. When measurement is needed, the system only needs to select and compare pre-computed values, enabling operation within a single clock period.
Solution Approach 2:
The patent implements periodic action through the SAR-ADC conversion process that operates in a systematic sequence: the capacitors are charged to represent different delay amounts, the ADC converts these voltages to digital values in a structured manner, and the results are made available for comparison. This periodic, structured conversion process ensures accurate phase difference measurement can be completed within one clock period, maintaining high intermittent operation rates.
3Measurement precision
If the TDC circuit operates continuously to detect phase differences accurately, then the detection accuracy is maintained, but the power consumption increases
Solution Approach 1:
The patent replaces the continuous operation of complex inverter-based delay circuits with an analog voltage representation system processed by a SAR-ADC. The delay line generates voltage levels that represent delay amounts, which are converted to digital values by the SAR-ADC. This substitution allows the system to achieve accurate phase difference detection with intermittent operation, significantly reducing power consumption compared to continuous digital circuit operation.
Solution Approach 2:
The SAR-ADC performs conversion in a periodic, structured manner, charging capacitors to represent delay voltages and converting them to digital values in sequence. This periodic action allows the system to maintain detection accuracy while operating intermittently rather than continuously, reducing power consumption by keeping the conversion circuit inactive during periods when phase difference detection is not required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a significant reduction in power consumption by allowing the current source to operate for only one clock period, independent of the phase difference magnitude, thereby enhancing the intermittent rate and reducing overall power usage.
Implementation Method 1
a SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current
Data Source
AI summary
The present technology relates to a phase-locked loop that allows a reduction in power consumption.A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.