Reconfigurable Fractional-N PLL with Selectable SDM Order
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Solution Overview
Problem
Existing electronic circuits require multiple reference oscillators to operate multiple transceivers at different line rates, leading to increased costs and resource consumption, and struggle with varying data reception accuracy requirements.
Innovation Solution
A reconfigurable fractional-N phase-locked loop (PLL) circuit using a single reference oscillator, incorporating a programmable sigma-delta modulator, frequency divider, and finite state machine for dynamic frequency band selection and high accuracy, allowing for fast acquisition and low jitter fractional synthesis across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple reference oscillators are used to operate multiple transceivers at different line rates, then each transceiver can achieve its required frequency accuracy, but the cost and resource consumption increase
Solution Approach 1:
A single reference oscillator is designed to serve multiple transceivers operating at different line rates through a reconfigurable fractional-N PLL architecture. The universal PLL circuit can be dynamically configured to generate different output frequencies by changing the divider ratio controlled by the sigma-delta modulator, eliminating the need for multiple dedicated reference oscillators while maintaining frequency accuracy requirements for each transceiver
Solution Approach 2:
The PLL circuit incorporates dynamic reconfiguration capability through a programmable sigma-delta modulator that can adjust the fractional divider ratio in real-time. This dynamic adjustment allows the single reference oscillator to adaptively generate different frequency outputs for different transceivers, transforming a static single-frequency system into a dynamic multi-frequency system that meets varying line rate requirements
2Quantity of substance
If a single reference oscillator is used to generate clocks for multiple transceivers, then resource usage is reduced, but achieving high frequency accuracy across different line rates becomes difficult
Solution Approach 1:
The system changes the divider ratio parameter dynamically using a fractional-N PLL approach with a programmable sigma-delta modulator. By varying the division ratio N in the feedback path while maintaining a stable reference frequency, the system can generate precise output frequencies for different transceivers. The fractional-N technique allows non-integer division ratios, enabling accurate frequency synthesis at multiple line rates from a single reference oscillator
Solution Approach 2:
The PLL incorporates a feedback mechanism where the output of the voltage-controlled oscillator is divided by N and fed back to the phase detector for comparison with the reference signal. This closed-loop feedback ensures that the output frequency remains locked to the reference frequency multiplied by the desired ratio, maintaining high frequency accuracy even when the divider ratio is reconfigured for different transceivers
3Adaptability or versatility
If fractional-N frequency synthesis is used to achieve flexible frequency generation, then adaptability improves, but loop bandwidth consistency and jitter performance deteriorate
Solution Approach 1:
The sigma-delta modulator is designed to be programmable with selectable orders (first, second, or third order), allowing the system to dynamically adjust the noise shaping characteristics based on the operating conditions. This dynamic reconfiguration of the modulator order enables optimization of the PLL performance for different frequency ranges and accuracy requirements, maintaining loop bandwidth consistency while preserving the adaptability benefits of fractional-N synthesis
Data Source
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AI summary
In an example, a phase-locked loop (PLL) circuit (108) includes an error detector (202) operable to generate an error signal; an oscillator (204) operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider (208) operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) (209) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine (214) operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.