PLL Time-to-Digital Converter With Segmented Delay Chains
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Solution Overview
Problem
The phase locking accuracy of phase-locked loops is relatively low due to the limitations of existing time-to-digital converters, which rely on delayers with large delay durations for accuracy but result in low detection accuracy and high error impacts.
Innovation Solution
A time-to-digital converter design that includes multiple delay chains with varying delay durations, where the first and third delay chains use delayers with longer durations and the second delay chain uses a delayer with a shorter duration, reducing the number of delayers required and improving detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If delayers with large delay durations are used in the delay unit, then the number of delayers required is reduced, but the detection accuracy deteriorates and error impact increases
Solution Approach 1:
The delay unit is segmented into multiple delay chains (first delay chain, second delay chain, third delay chain) with different delay durations. Each chain contains delayers with specific delay characteristics, allowing the system to divide the phase detection task across multiple specialized paths rather than using a single uniform delay structure.
Solution Approach 2:
Different delay chains are assigned different delay durations tailored to their specific functions. The first and third delay chains use delayers with longer delay durations for coarse phase comparison, while the second delay chain uses delayers with shorter delay durations for fine phase comparison, optimizing each local region for its specific purpose.
2Measurement precision
If delayers with small delay durations are used, then detection accuracy is improved, but the number of delayers required increases and cumulative error impact increases
Solution Approach 1:
The system segments the phase detection function across multiple delay chains with different delay characteristics. By dividing the task into coarse detection (first and third chains) and fine detection (second chain), the system avoids the need for a large number of small-delay delayers while maintaining high accuracy.
Solution Approach 2:
The invention changes the delay duration parameter across different delay chains rather than using uniform delayers. This parameter variation allows the system to achieve high detection accuracy with fewer total delayers by optimizing each chain's delay characteristic for its specific detection range.
3Measurement precision
If multiple delay chains with varying delay durations are used, then detection accuracy is enhanced and phase noise is reduced, but device complexity increases
Solution Approach 1:
The delay unit is divided into three distinct delay chains, each performing a specific function in the phase detection process. This segmentation allows parallel processing of different phase comparison tasks, improving accuracy while keeping each individual chain relatively simple.
Solution Approach 2:
Multiple delay chains with different delay characteristics are merged into a unified phase detection system. The outputs from all three delay chains are combined through the sampling unit to produce the final phase difference measurement, leveraging the strengths of each chain to achieve superior overall performance.
Data Source
AI summary
A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal.