Segmented PLL Phase Tracking Loop for Jitter Rejection
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Solution Overview
Problem
Existing phase locked loop (PLL) devices face limitations in clock recovery applications due to excessive peaking and limited bandwidth, leading to poor jitter rejection and increased power consumption, which affects the performance of clock generation and extraction processes.
Innovation Solution
The proposed solution involves emulating a voltage-controlled oscillator (VCO) in a digital control loop, splitting feedback loop control into proportional and integral paths, using a phase rotator and a digital accumulator for frequency tracking, and a fine digitally controlled delay element for phase tracking, to decouple high bandwidth requirements for phase noise rejection from clock recovery bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL control is used, then clock recovery is achieved, but jitter rejection is poor and peaking is excessive
Solution Approach 1:
The feedback control is segmented into two independent paths: a high-bandwidth proportional path for phase noise rejection and a low-bandwidth integral path for frequency tracking. This segmentation allows each path to be optimized for its specific function, resolving the contradiction between jitter rejection and peaking by preventing the integral path from limiting the proportional path's bandwidth.
Solution Approach 2:
A digital accumulator is introduced as an intermediary component in the integral path to perform frequency tracking. This intermediary allows the system to maintain separate control loops with different bandwidth characteristics, enabling the proportional path to operate at high bandwidth for jitter rejection while the integral path operates at low bandwidth to avoid peaking.
2Reliability
If high bandwidth is used for phase noise rejection, then jitter rejection improves, but clock recovery bandwidth is limited
Solution Approach 1:
The control bandwidth is segmented into two distinct ranges: the proportional path handles high-frequency phase noise rejection with high bandwidth, while the integral path handles low-frequency frequency tracking with low bandwidth. This segmentation resolves the contradiction by allowing each path to operate in its optimal bandwidth range without interfering with the other.
3Reliability
If conventional PLL structure is used, then clock synchronization is achieved, but power consumption is high
Solution Approach 1:
The conventional analog VCO control is replaced with a digital control system using a digital accumulator and segmented digital control paths. This substitution reduces power consumption by eliminating analog circuitry while maintaining clock synchronization through digital signal processing in the proportional and integral paths.
4Reliability
If conventional PLL structure is used, then clock synchronization is achieved, but die area is large
Solution Approach 1:
The analog PLL components are replaced with digital implementations, including a digital accumulator and digital control logic for the segmented proportional and integral paths. This digital substitution reduces die area by eliminating large analog circuitry while achieving clock synchronization through compact digital signal processing elements.
Data Source
AI summary
Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.