PLL Oscillator Self-Calibration Using Phase Detector Error Signals
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits require factory testing and permanent trimming of voltage-controlled oscillators (VCOs), limiting their frequency range and increasing manufacturing costs, while existing self-calibration methods often require additional components or additional phase/frequency detectors, and are inefficient due to charging times or complex calibration processes.
Innovation Solution
A self-calibrating PLL circuit that uses error signals from the phase/frequency detector to automatically trim the VCO to the appropriate operating curve during power-up, allowing reuse across different applications without permanent trimming, and achieves this with minimal additional components, using a state machine and switches to select the correct trim setting based on phase differences between input and feedback signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If factory testing and permanent trimming of VCOs is performed, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by performing VCO trimming automatically during power-up calibration instead of during factory manufacturing. The calibration circuit proactively adjusts the VCO frequency by applying trimming voltages based on phase detector error signals before the device is put into service, eliminating the need for complex factory testing and permanent trimming processes.
2Manufacturing precision
If permanent trimming is applied to VCO, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements dynamics by making the VCO trimming setting changeable rather than fixed. The calibration circuit can dynamically adjust the VCO frequency by applying different trimming voltages during calibration, and the trimmed setting can be re-calibrated for different frequency ranges, enabling the same device to adapt to multiple applications and frequency requirements.
3Measurement precision
If additional phase/frequency detectors are used for self-calibration, then calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by making the existing phase detector serve dual functions: it operates as the normal phase detector during PLL operation and as a frequency measurement device during calibration. The same phase detector compares the VCO output frequency with the reference frequency during calibration, eliminating the need for additional dedicated frequency measurement detectors or counters.
Solution Approach 2:
The patent merges the calibration function with the existing PLL components. The phase detector, charge pump, and loop filter are reused during calibration instead of creating separate calibration circuits. The calibration process integrates the VCO trimming control with the existing charge pump current control mechanism, combining multiple functions into unified circuit operations.
4Measurement precision
If charge pump charging time is required for calibration, then calibration accuracy is improved, but productivity deteriorates
Solution Approach 1:
The patent implements continuity of useful action by maintaining the charge pump in a continuously active state during calibration, avoiding repeated charging and discharging cycles. The charge pump continuously supplies current to the loop filter capacitor, allowing the trimming voltage to be adjusted and applied without interruption, thereby achieving both accurate calibration and fast calibration speed.
Data Source
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Figure 3
Figure 4A~4B
AI summary
A phase-locked loop circuit comprises an oscillator (308) having a plurality of operating curves and being suitable for generating an output signal (FOSC). In a calibration state the oscillator (308) is trimmed to an operating curve for use in a normal operation state. The phase-locked loop circuit further comprises a phase/frequency detector (302) being suitable for generating at least one error signal (FE) based on an input signal (FIN) and a feedback signal (FDIV) generated on the basis of the output signal (FOSC). The phase-locked loop circuit further comprises a loop filter (303) being suitable for generating a loop-filter signal (VLF) based on the at least one error signal (FE, UP, DOWN), the loop-filter signal (VLF) being applied to the oscillator (308) in the normal operation state. The phase-locked loop circuit further comprises a calibration circuit (312) being suitable for trimming the oscillator (308) to the operating curve for use in the normal operation state on the basis of the at least one error signal.