PLL Self-Test Circuit for Phase Noise and Jitter Measurement
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Solution Overview
Problem
Conventional methods for testing phase noise or jitter in electrical systems, such as communication and RADAR systems, require expensive automated test equipment and are inefficient for mass production, as they cannot accurately measure ultra-low phase noise performance and do not account for aging effects.
Innovation Solution
A system utilizing a pair of identical phase-coherent phase-locked loops (PLLs) with a mixer and analog-to-digital converter (ADC) to measure phase noise and jitter by mixing their outputs and performing digital post-processing, which can be integrated into devices for self-testing, eliminating the need for high-end ATE equipment and allowing for phase noise measurement at any time, including during device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional automated test equipment (ATE) is used to measure phase noise, then measurement capability is provided, but the equipment cost becomes excessively high and measurement time becomes prohibitively long
Solution Approach 1:
The patent creates a simplified copy of the measurement system by using a second PLL as a reference instead of expensive external equipment. This reference PLL generates a clean clock signal that serves as a local reference, eliminating the need for high-end ATE while maintaining measurement capability through the mixing and FFT process
Solution Approach 2:
The system performs self-testing by using its own internal resources - a second PLL is included specifically to serve as a reference oscillator for measuring the first PLL's phase noise. This built-in reference eliminates dependency on external expensive equipment and enables continuous monitoring during normal operation
2Measurement precision
If conventional testing methods are used, then phase noise measurement is performed, but aging effects cannot be accounted for and testing cannot occur during device operation
Solution Approach 1:
The patent enables continuous phase noise measurement during normal device operation. The second PLL runs concurrently as a reference while the first PLL performs its normal function, allowing phase noise to be monitored continuously throughout the device's operational lifetime, thereby capturing aging effects that occur during actual use
Solution Approach 2:
The patent uses a second PLL with comparable (not superior) phase noise performance as a reference, accepting that this reference will eventually age and degrade. This practical approach acknowledges that even reference oscillators have finite lifetimes but provides sufficient measurement capability for the operational period, replacing the reference PLL when needed
3Productivity
If mass production testing is performed with conventional equipment, then production throughput is maintained, but the testing process becomes prohibitively expensive and time-consuming
Solution Approach 1:
The patent replaces expensive external ATE equipment with an internal reference PLL copy, dramatically reducing per-unit testing cost and time. The reference PLL and mixing circuitry can be integrated into the device itself, enabling rapid self-testing during or after assembly without requiring specialized external measurement equipment
Solution Approach 2:
The patent combines the reference oscillator function with the measurement function by using a second PLL that serves both as a clock source and a reference for phase noise measurement. This merging eliminates the need for separate expensive measurement equipment and reduces testing time by performing measurements in-integration with normal device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective and efficient phase noise and jitter testing, reducing production time and costs, while also accounting for aging effects, by using a built-in self-test module that can perform phase noise and jitter measurements without expensive equipment, ensuring reliable performance over the device's lifetime.
Implementation Method 1
a mixer configured to mix the first clock signal with a second clock signal
Data Source
AI summary
A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.