PLL Frequency Calibration and Lock Detection With Shared Error Circuit
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Solution Overview
Problem
Existing semiconductor systems face challenges in synchronizing the operating speeds of processors with peripheral devices, leading to inefficiencies in data transmission due to speed differences, which is exacerbated by the large circuit area required for automatic frequency calibration and lock detection circuits.
Innovation Solution
The implementation of an automatic frequency calibration and lock detection circuit that shares components, specifically a frequency error generator circuit, to reduce circuit area and improve synchronization by generating calibration and lock signals efficiently within a phase locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate frequency error generator circuits are used for automatic frequency calibration and lock detection, then the reliability and functionality are improved, but the circuit area increases significantly
Solution Approach 1:
The patent combines the frequency error generator circuits for automatic frequency calibration and lock detection into a single shared circuit. The frequency error generator generates frequency error signals that are simultaneously used by both the automatic frequency calibration signal generator and the lock flag generator, thereby reducing circuit area while maintaining the functionality and reliability of both operations.
Solution Approach 2:
The shared frequency error generator circuit serves multiple functions by generating frequency error signals that are utilized by both the automatic frequency calibration process and the lock detection process. This multi-functional design eliminates the need for separate dedicated circuits for each operation, achieving area reduction without compromising the reliability of either function.
2Productivity
If high transmission frequency is used to improve data transmission speed, then the productivity is improved, but the synchronization difficulty and circuit complexity increase
Solution Approach 1:
The patent employs feedback mechanisms where the frequency error signals generated by the shared frequency error generator are continuously used to adjust and synchronize the output frequency. This feedback loop enables accurate frequency synchronization even at high transmission frequencies, allowing high data transmission speeds while managing synchronization complexity through automated frequency calibration and lock detection.
Data Source
AI summary
An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.