PLL Calibration Using a Shared Phase Detector for Gain and Duty Cycle
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in calibrating loop gain and duty cycle due to variations in process, voltage, and temperature (PVT), leading to sub-optimal phase noise performance and complexity in simultaneous calibration.
Innovation Solution
Implementing a PLL with a phase detector that receives delayed reference and feedback signals to output an error signal, allowing for concurrent gain and duty cycle calibration using shared phase detection, reducing system complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate phase detectors are used for gain calibration and duty cycle calibration, then calibration accuracy is improved, but device complexity and area increase
Solution Approach 1:
The patent implements a single phase detector that serves multiple calibration functions by switching between different calibration modes. The phase detector is configured to perform both gain calibration and duty cycle calibration sequentially, eliminating the need for separate detectors while maintaining calibration accuracy through mode switching control
Solution Approach 2:
The patent combines gain calibration and duty cycle calibration functions into a unified calibration system using one shared phase detector. The calibration controller coordinates both calibration processes through the single detector, merging previously separate functions into one integrated solution that reduces area and complexity
2Loss of time
If simultaneous gain calibration and duty cycle calibration are performed, then calibration time is reduced, but system complexity increases
Solution Approach 1:
The patent implements periodic alternating calibration cycles where the single phase detector switches between gain calibration mode and duty cycle calibration mode. The calibration controller manages these periodic switching operations, allowing both calibration functions to be performed in sequence within a unified time framework, reducing total calibration time while avoiding simultaneous operation complexity
3Measurement precision
If direct loop gain measurement is used for calibration, then calibration precision is improved, but practical implementation becomes difficult
Solution Approach 1:
The patent introduces an intermediary calibration approach where the phase detector measures phase differences and pulse width differences as indirect indicators of loop gain and duty cycle conditions. Instead of directly measuring loop gain, the system uses these accessible phase-related measurements to infer and adjust calibration parameters, making implementation practical while maintaining precision
4Measurement precision
If static phase offset correction is applied to improve duty cycle detection accuracy, then duty cycle measurement precision is improved, but PLL output disturbance increases
Solution Approach 1:
The patent performs static phase offset characterization and correction in advance during the calibration phase, before normal PLL operation begins. The offset values are measured and stored as calibration data, allowing the system to compensate for phase offset effects without applying real-time corrections that would disturb ongoing PLL operation. This preliminary characterization eliminates measurement errors without causing operational disturbances
Data Source
AI summary
This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.