High-Bandwidth PLL Sideband Rejection Using Frequency Estimation
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Solution Overview
Problem
Current Phase Lock Loop (PLL) circuits face challenges in high noise environments, where they may inaccurately lock onto undesired signals or sideband noise, compromising precision and accuracy, and reducing gain to prevent this reduces frequency response and tracking ability.
Innovation Solution
A PLL circuit system that uses a gyroscope and a phase lock loop with a control circuit to generate an estimation signal within a defined frequency range, preventing phase locking on undesired signals by comparing the beat note signal with the estimation signal and adjusting the numerically controlled oscillator to ensure accurate locking onto the desired target signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gain is reduced to prevent locking on undesired signals, then accuracy is preserved, but precision and frequency response deteriorate
Solution Approach 1:
The patent applies preliminary action by performing frequency estimation and range determination before the PLL locking process. The control circuit预先 determines a frequency range based on estimated parameters, and only allows the PLL to search within this constrained range. This prevents the PLL from locking on to undesired signals outside the range while maintaining high gain for rapid tracking, thus resolving the contradiction between accuracy and frequency response.
2Speed
If PLL circuit indiscriminately locks on to the largest signal, then locking speed is fast, but accuracy deteriorates due to potential locking on undesired signals
Solution Approach 1:
The patent changes the parameter space by introducing frequency estimation and range determination. Instead of allowing the PLL to search the entire frequency spectrum, the control circuit calculates an estimated frequency and defines a constrained search range around this estimate. This parameter transformation allows the PLL to maintain fast locking speed within the constrained range while avoiding undesired signals outside the range, thus resolving the accuracy-speed contradiction.
3Reliability
If gain is reduced to narrow the search path, then risk of locking on undesired signals is reduced, but tracking ability deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the frequency search space into segments based on the estimated frequency and determined range. The PLL is constrained to search only within the relevant frequency segment rather than the entire spectrum. This segmentation maintains reliability by preventing locks on undesired signals in other segments, while preserving tracking ability within the relevant segment through maintained gain settings.
Data Source
AI summary
In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.