PLL Reference Signal Failover for Stable Frequency Output
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Solution Overview
Problem
Conventional PLL circuits face challenges in maintaining frequency stability when an external reference frequency signal is disrupted, leading to fluctuations in output frequency, which is critical in applications like mobile communication base stations and broadcasting stations.
Innovation Solution
A PLL apparatus that includes a voltage-controlled oscillation unit, phase difference data creation, an output mechanism for control voltage, storage for phase difference data, monitoring of signal levels, and switching to use stored data when signal levels fall outside a set range, utilizing orthogonal transformation and angular velocity calculation to stabilize frequency output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional PLL circuit uses an external reference frequency signal for phase comparison, then frequency accuracy can be maintained under normal conditions, but frequency stability deteriorates when the external reference signal disappears or its level decreases
Solution Approach 1:
The patent stores phase difference data in advance in a storage unit (memory) before the external reference signal fails. When the signal disappears or its level decreases, the stored phase difference data is used to generate the control voltage, avoiding frequency jumps and maintaining stability without requiring real-time external signal processing.
Solution Approach 2:
The patent introduces a monitoring unit that detects the level of the external reference signal and a switching unit that selects between real-time phase difference data and stored phase difference data. This intermediary mechanism automatically transitions the PLL circuit from using external reference to using stored data when the external signal becomes unreliable, resolving the contradiction between accuracy and stability.
2Adaptability or versatility
If the PLL circuit relies on real-time external reference signal for phase comparison, then it can track frequency changes, but it becomes vulnerable to signal disappearance and level fluctuations causing output frequency jumps
Solution Approach 1:
The patent prepares stored phase difference data in advance as a cushion against future signal failures. This pre-stored data acts as a buffer that protects the PLL circuit from the harmful effects of external signal disappearance or fluctuation, ensuring continuous stable operation without frequency jumps.
Solution Approach 2:
The monitoring unit continuously monitors the external reference signal level and provides feedback to the switching unit. When the signal level falls outside the predetermined range, the feedback triggers the switching unit to select stored phase difference data, creating a closed-loop protection mechanism that automatically responds to signal quality changes.
Data Source
AI summary
Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a troubleFor solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.