PLL Signal Synchronization Circuit for Manufacturing Variation Tolerance
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Solution Overview
Problem
Conventional signal synchronization circuits face challenges in quantitatively accounting for manufacturing variations between different clock synchronization systems, leading to potential anomalies during device inspection in mass production.
Innovation Solution
A semiconductor device with a signal synchronization circuit that includes a phase-locked loop (PLL) circuit and flip-flops, where the setup time for synchronization is set to half the period of the reference clock signal, allowing for effective signal conversion between differing clock systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay element is interposed between flip-flops of one system and flip-flops of another system to ensure setup time and hold time, then signal synchronization between different clock systems is achieved, but manufacturing variation between the two systems cannot be quantitatively known at the design stage, leading to potential anomalies during device inspection in mass production
Solution Approach 1:
The patent changes the setup time parameter from a fixed value to a variable that is dynamically adjusted based on the actual delay characteristics of the delay element. The setup time is set to be longer than the maximum delay of the delay element, allowing the synchronization circuit to adapt to manufacturing variations. This parameter adjustment enables the circuit to maintain reliable synchronization while accommodating the unknown manufacturing variations between different clock systems.
2Device complexity
If the setup time is set to a fixed value, then the circuit design is simple, but it cannot accommodate manufacturing variations between different clock systems, causing operational tolerance to decrease
Solution Approach 1:
The patent introduces dynamic adjustment capability to the setup time parameter. Instead of using a fixed setup time value, the circuit can dynamically adjust the setup time based on the actual delay characteristics of the delay element. This dynamic approach allows the circuit to maintain optimal synchronization performance across different manufacturing variations while keeping the overall circuit structure relatively simple.
3Reliability
If delay elements are used to compensate for clock skew and delay between flip-flops, then signal synchronization is improved, but the circuit becomes more sensitive to manufacturing variations between clock systems
Solution Approach 1:
The patent implements a feedback mechanism where the delay characteristics of the delay element are measured or estimated, and this information is used to adjust the setup time parameter. The feedback loop allows the circuit to compensate for manufacturing variations by adapting the setup time to the actual delay characteristics, thereby reducing sensitivity to manufacturing variations while maintaining reliable signal synchronization.
Data Source
AI summary
A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.