PLL Realignment Path With Skew Cancellation for Lock Stability
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Solution Overview
Problem
Phase locked loops (PLLs) used for high-speed clock signals often experience anomalous behavior due to phase noise and spurious signals, leading to suboptimal output from voltage controlled oscillators (VCOs), which can break the locked condition over time.
Innovation Solution
Implementing a realignment path with clock realignment signals generated by a pulse generator, utilizing skew mitigation circuitry to align with the current state of the PLL and VCO, and using identical logic gates to maintain the locked condition, avoiding the need for programmable delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a realignment path with clock realignment signals is implemented to maintain the locked condition, then the stability and reliability of the PLL is improved, but the device complexity increases due to additional circuitry
Solution Approach 1:
The patent combines the realignment path with the existing PLL circuitry by using the same phase/frequency detector outputs to generate both the charge pump control signals and the clock realignment signals. This merging approach maintains reliability through realignment functionality while avoiding the need for completely separate, additional circuit blocks that would increase complexity.
Solution Approach 2:
The phase/frequency detector serves multiple functions: it generates both the UP/DN control signals for the charge pump and the realignment signals for the clock generator. This multi-functionality allows the realignment feature to be implemented without adding dedicated realignment detection circuitry, thereby improving reliability while minimizing the increase in device complexity.
2Measurement precision
If skew mitigation circuitry is used to align realignment signals with PLL and VCO state, then the timing precision and accuracy are improved, but the device complexity increases due to additional alignment logic
Solution Approach 1:
The patent applies skew mitigation by pre-calculating and pre-adjusting the timing of realignment signals based on known skew characteristics of the circuit paths. The alignment logic determines the appropriate skew compensation in advance and applies it systematically, improving timing precision without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The skew mitigation circuitry adjusts timing parameters of the realignment signals by modifying their phase or delay characteristics. By changing these temporal parameters based on predetermined skew values, the system achieves precise signal alignment while using relatively simple delay or phase adjustment circuitry rather than complex adaptive systems.
3Manufacturing precision
If identical logic gates are used in the realignment path, then the manufacturing precision and consistency are improved, but the adaptability decreases due to lack of programmable delay lines
Solution Approach 1:
The patent uses identical logic gates in critical paths where consistency is paramount (such as the realignment signal generation path) to ensure manufacturing precision and circuit behavior consistency. At the same time, it incorporates programmable delay elements in specific locations where timing adjustment flexibility is needed, applying different quality requirements to different parts of the circuit based on their functional needs.
Solution Approach 2:
The system combines static identical logic gates for consistent baseline behavior with dynamic programmable delay lines that can be adjusted during operation. This dynamic element allows the circuit to adapt timing characteristics as needed while maintaining the manufacturing precision benefits of using identical logic gates in the core realignment path.
Data Source
AI summary
Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.