PLL Slip Detection Circuit for Noise-Induced Phase Deviations
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Solution Overview
Problem
Phase-locked loops (PLLs) are susceptible to noise, leading to phase deviations between input and output clocks, which can cause downstream electronics to malfunction, and existing solutions fail to effectively detect and correct such deviations in a timely manner.
Innovation Solution
A phase-locked loop (PLL) with a phase-frequency detector, low pass filter, flip-flop, and lock-slip control circuit that generates signals to determine phase-lock and phase-slip conditions, using a configurable low-pass filter and counters to detect phase differences and assert LOCK and QUASI SLIP signals to indicate lock or slip states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is used to generate output clock signals, then clock generation functionality is provided, but phase deviations between input and output clocks occur due to noise susceptibility
Solution Approach 1:
The patent applies preliminary action by detecting phase slips before they cause downstream electronics to malfunction. The lock-slip control circuit continuously monitors the phase relationship between input and output clocks using a phase-frequency detector and low-pass filter, asserting LOCK and QUASI SLIP signals in advance to indicate lock or slip states, allowing corrective action to be taken before actual phase deviations affect downstream circuitry.
Solution Approach 2:
The patent implements feedback through the lock-slip control circuit that continuously compares the output clock phase with the input reference clock phase. The phase-frequency detector generates signals based on phase differences, the low-pass filter processes these signals, and the lock-slip control circuit asserts feedback signals (LOCK and QUASI SLIP) that indicate the current lock state, enabling continuous correction to maintain phase-lock stability.
2Measurement precision
If existing detection solutions are used, then some phase deviation detection is provided, but phase slips are not detected and corrected in a timely manner
Solution Approach 1:
The patent applies preliminary action by detecting phase slips before they cause downstream electronics to malfunction. The lock-slip control circuit continuously monitors the phase relationship between input and output clocks using a phase-frequency detector and low-pass filter, asserting LOCK and QUASI SLIP signals in advance to indicate lock or slip states, allowing corrective action to be taken before actual phase deviations affect downstream circuitry.
Solution Approach 2:
The patent replaces complex mechanical or analog phase detection mechanisms with a streamlined electronic detection system consisting of a phase-frequency detector, low-pass filter, and digital lock-slip control circuit. This substitution enables faster detection response by using electronic signal processing rather than mechanical measurement methods, reducing the time loss associated with detecting and responding to phase slips.
Data Source
AI summary
A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.