PLL Slip Detection Circuit for Noise-Induced Phase Deviations
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Solution Overview
Problem
Phase-locked loops (PLLs) are susceptible to noise, which can cause large phase deviations between input and output clocks, leading to undesirable behaviors in downstream electronics, and existing solutions fail to effectively detect and manage these deviations.
Innovation Solution
A phase-locked loop (PLL) with a phase-frequency detector, low pass filter, flip-flop, and lock-slip control circuit that generates signals to determine phase-lock and phase-slip conditions, using a configurable low-pass filter and counters to detect slip states and generate indicative signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is used to generate output clock signals, then phase relationship control is achieved, but noise susceptibility causes phase deviations that lead to undesirable behaviors in downstream electronics
Solution Approach 1:
The patent implements preliminary detection of phase slips by monitoring the phase relationship between reference and output clocks before they cause harmful effects in downstream electronics. The slip detector circuit proactively identifies phase deviations and generates warning signals, allowing the system to take preventive measures before noise-induced phase errors affect downstream circuitry.
Solution Approach 2:
The patent employs feedback mechanisms where the slip detector continuously monitors the phase relationship and feeds back slip detection signals to the control logic. This feedback loop enables real-time adjustment and correction of phase deviations, improving the reliability of phase lock by constantly comparing the actual phase relationship with the desired relationship and making corrective adjustments.
2Measurement precision
If existing PLL solutions are used, then basic phase locking is achieved, but they fail to effectively detect and manage phase deviations
Solution Approach 1:
The patent segments the phase detection function into distinct components: a phase-frequency detector for basic phase locking, a separate slip detector circuit for detecting phase slips, and control logic for managing slip states. This segmentation allows each component to specialize in its specific function, improving measurement precision for phase deviation detection while maintaining ease of operation through modular design where each segment handles a specific aspect of phase management.
Solution Approach 2:
The patent introduces an intermediary slip detector circuit that acts as a mediator between the phase-frequency detector and the downstream electronics. This intermediary component specifically detects phase slips and generates intermediate signals that facilitate easier management of slip states, bridging the gap between basic phase locking functionality and sophisticated slip management requirements.
3Reliability
If phase deviations are not detected, then the PLL operates simply, but large phase differences cause undesirable behaviors in downstream electronics
Solution Approach 1:
The patent applies local quality by implementing a dedicated slip detection mechanism specifically targeted at detecting large phase deviations, while the rest of the PLL maintains its standard simple structure for normal phase locking operations. This localized addition of detection capability ensures reliable operation of downstream electronics by specifically monitoring for harmful phase slips without requiring a complete redesign of the entire PLL architecture.
Solution Approach 2:
The slip detector circuit performs preliminary detection of potentially harmful phase deviations before they affect downstream electronics. By proactively identifying phase slips early in the signal path, the system can take corrective action before large phase differences cause undesirable behaviors, maintaining reliability without requiring complex post-detection correction mechanisms.
Data Source
AI summary
A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.