PLL Clock Circuit With Split Control Paths for Noise Suppression

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Solution Overview

Problem

Existing clock signal generating circuits, such as phase-locked loops (PLLs), face challenges in design flexibility and noise suppression due to the interdependence of circuit parameters like charge pump currents, oscillator gain, and filter capacitance and resistance, limiting their performance.

Innovation Solution

A clock generating circuit architecture that includes separate integral and proportional paths with charge pumps and a bias path with a low-pass filter, allowing for independent control of the oscillator's gain and noise reduction through the generation of multiple control signals to control the voltage-controlled oscillator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If circuit parameters (charge pump currents, oscillator gain, filter capacitance and resistance) are adjusted to improve performance, then the PLL can achieve different performance characteristics, but the area of the circuit and the noise of the signal are greatly affected

Engineering Contradiction:

ImproveperformanceVSAvoidnoise

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the control signal generation into three separate paths (integral path, proportional path, and bias path), each with its own charge pump and control mechanism. This segmentation allows independent optimization of each path's parameters without affecting the others, enabling performance improvement while controlling noise impact on the overall circuit

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If circuit parameters are adjusted to achieve different performance, then the PLL can be optimized for specific applications, but the design flexibility is limited due to parameter interdependence

Engineering Contradiction:

Improvedesign flexibilityVSAvoidparameter interdependence

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the control signal generation into three independent paths with separate charge pumps and control mechanisms. This allows each path to be independently designed and optimized without being constrained by parameter interdependence in traditional single-path PLL designs

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic control capabilities by allowing different charge pump currents and filter configurations in each path, enabling the system to adapt to different performance requirements while maintaining design flexibility through independent parameter adjustment

Inventive Principle:

Principle #15Dynamics

3Speed

If the gain of the voltage-controlled oscillator is increased to improve frequency adjustment range, then the frequency tuning capability is enhanced, but noise interference is also amplified

Engineering Contradiction:

Improvefrequency adjustment rangeVSAvoidnoise interference

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different filter characteristics and charge pump current levels in different paths, with the bias path providing a stable DC operating point that reduces noise sensitivity. This allows the VCO to operate at higher gain settings for broader frequency range while the localized noise reduction in the bias path prevents overall noise amplification

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This architecture provides increased design freedom and effectively suppresses noise interference by allowing for flexible adjustment of the voltage-controlled oscillator's gain and currents, while maintaining a large frequency adjustment range.

Implementation Method 1

a low-pass filter within the bias path filters the first control signal to generate a third control signal

Methodology Applied

Scientific EffectLow-pass filtering: Filter (electronic)

Data Source

PatentUS10819350B2Clock signal generating circuit and method for generating clock signal

Publication Date: 2020.10.27 REALTEK SEMICON CORP

AI summary

The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.