PLL Spread Spectrum Transition Circuit for Stable Clock Switching
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Solution Overview
Problem
Conventional clock signal generation circuits experience overshoot and undershoot during transitions from non-spread spectrum to spread spectrum mode due to direct changes in PLL divider values, leading to system failures.
Innovation Solution
A control block is introduced to synchronously load intermediate values for the PLL, allowing it to lock to a predetermined center frequency before transitioning to spread spectrum mode, thereby reducing overshoot and undershoot by providing a waiting period for stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If spread spectrum modulation is turned on directly from non-spread spectrum mode, then the system enters spread spectrum mode, but frequency overshoot and undershoot occur causing system failure
Solution Approach 1:
The patent applies preliminary action by loading intermediate M and N values into the dividers before actually enabling spread spectrum modulation. This preparatory step allows the PLL to begin adjusting to the new center frequency in advance, so that when spread spectrum mode is fully activated, the frequency transition is already stabilized and overshoot/undershoot is minimized.
Solution Approach 2:
The patent segments the mode transition process into distinct phases: first loading intermediate divider values (M_intermediate, N_intermediate) to shift the center frequency partially, then enabling spread spectrum modulation after this intermediate stabilization. This segmentation breaks the abrupt direct transition into controlled steps, preventing frequency excursions that would cause system failure.
2Speed
If PLL divider values are changed directly to new center frequency, then the transition to spread spectrum mode is achieved, but frequency overshoot and undershoot occur
Solution Approach 1:
The frequency transition is segmented into two stages: first transitioning to an intermediate center frequency using intermediate M and N values, then completing the transition to the final spread spectrum center frequency. This staged approach maintains frequency accuracy by avoiding direct large-step changes that cause overshoot, while still achieving the transition goal.
Solution Approach 2:
The patent introduces intermediate M and N values as mediator parameters between the non-spread spectrum and full spread spectrum modes. These intermediate values serve as a bridge, allowing the PLL to transition through a middle frequency state that stabilizes the phase lock before the final frequency adjustment, thereby preventing frequency excursions.
3Reliability
If intermediate values are loaded into PLL dividers, then frequency overshoot and undershoot are reduced, but transition time increases due to waiting period
Solution Approach 1:
The patent performs preliminary frequency adjustment by loading intermediate divider values before enabling spread spectrum modulation. This preliminary action stabilizes the PLL at an intermediate frequency, and the subsequent enabling of spread spectrum mode occurs from this stabilized state, minimizing the need for extended waiting periods and reducing overall transition time while maintaining frequency stability.
Data Source
AI summary
An apparatus and a method to initiate spread spectrum modulation have been presented. In one embodiment, a spread spectrum off to spread spectrum on transition circuit is used to start spread spectrum modulation. The spread spectrum off to spread spectrum on transition circuit may include a phase lock loop (PLL) to output a clock signal. The spread spectrum off to spread spectrum on transition circuit may further include a control block coupled to the PLL to cause the PLL to lock the clock signal to a predetermined center frequency before transitioning from a non-spread spectrum mode into a spread spectrum mode.