Fractional-N PLL Compensation Circuit for Reference Spur Elimination
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Solution Overview
Problem
Radio-frequency (RF) systems face issues with phase noise and spurious tones, specifically reference spurs, in fractional-N frequency synthesis, which affect signal stability and purity.
Innovation Solution
A phase-locked loop (PLL) circuit with a compensation circuit that generates a compensation signal to eliminate reference spurs, utilizing a charge pump, loop filter, and voltage-controlled oscillator (VCO) to modulate the charge pump current based on phase differences, ensuring the charge pump pulse has a constant width and amplitude, thereby reducing or eliminating spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase-locked loop (PLL) is used for frequency synthesis in RF systems, then the desired operating frequency can be generated, but reference spurs and phase noise are introduced that degrade signal purity
Solution Approach 1:
The patent extracts and removes the harmful reference spur components from the PLL output signal by introducing a compensation signal that is specifically designed to cancel these spurs. The compensation circuit identifies the reference spur frequencies and generates counter-signals to eliminate them, thereby improving signal purity while maintaining the frequency synthesis function.
Solution Approach 2:
The patent converts the harmful reference spurs into a beneficial cancellation mechanism. By detecting the reference spur components and generating compensation signals with opposite phase, the system transforms the harmful spurs into a self-correcting feature where the spurs themselves provide the information needed to create their own cancellation signal.
2Adaptability or versatility
If fractional-N frequency synthesis is used to achieve flexible frequency tuning, then frequency adaptability is improved, but reference spurs are generated that affect signal stability
Solution Approach 1:
The patent implements a feedback mechanism where the output signal is monitored for reference spur components, and a compensation signal is generated and fed back into the PLL to cancel these spurs. This closed-loop feedback system continuously adjusts the compensation to maintain signal stability while preserving the frequency tuning flexibility of fractional-N synthesis.
Solution Approach 2:
The patent changes the parameters of the charge pump current by modulating its amplitude based on the detected phase differences, while maintaining a substantially constant pulse width. This parameter modification allows the system to generate compensation signals that cancel reference spurs without disrupting the frequency tuning capability, thereby maintaining both adaptability and stability.
3Measurement precision
If the charge pump pulse width is made constant to reduce spurs, then signal purity is improved, but the ability to respond to phase differences is reduced
Solution Approach 1:
The patent moves the phase difference information from the time domain (pulse width) to the amplitude dimension. By keeping the pulse width constant and instead modulating the amplitude of the charge pump current based on phase differences, the system maintains signal purity while preserving the ability to respond to phase variations through amplitude modulation rather than width modulation.
Data Source
AI summary
Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.