PLL Reference Frequency Switching for Fractional-N Spur Reduction
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Solution Overview
Problem
Conventional phase locked loops (PLLs) in communication systems face issues with spurs when generating non-integer multiple frequency signals, leading to reduced signal-to-noise ratio (SNR) and bit error rate (BER), particularly due to sidebands caused by fractional-N synthesizers.
Innovation Solution
A fractional-N synthesizer with a phase locked loop topology and a multi-modulus divider, combined with a spur reduction module that adjusts the reference signal frequency to move spurs outside the passband, using a switching module to select between input and processed signals, and a modulator to generate a randomized integer sequence for fine-tuning, thereby reducing spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a non-integer value is utilized by the divider to generate the feedback signal, then the PLL can provide a system output signal having a frequency that is a non-integer multiple of the reference signal frequency, but spurs are generated that reduce the signal-to-noise ratio and degrade the bit error rate
Solution Approach 1:
The patent employs periodic switching between different reference signal frequencies (first and second reference frequencies) to generate the feedback signal. This periodic action allows the system to achieve non-integer multiplication ratios while distributing spurs across different frequency positions, reducing their impact on any single frequency and thereby improving the signal-to-noise ratio and bit error rate.
2Manufacturing precision
If an integer value is utilized by the divider to generate the feedback signal, then the system output signal frequency is an integer multiple of the reference signal frequency, but the frequency tuning resolution is limited
Solution Approach 1:
The patent dynamically switches between different reference signal frequencies based on the desired output frequency requirements. By changing the reference frequency dynamically, the system can achieve fine frequency resolution while maintaining integer multiplication ratios, thus resolving the contradiction between frequency precision and tuning range.
Data Source
AI summary
A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.