Multi-Phase Signal Generation With PLL-Stable Phase Mode Switching
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Solution Overview
Problem
Existing multi-phase signal generation systems face challenges in transitioning between different phase modes, such as eight-phase and four-phase signals, due to indeterministic phase shifts and changes in load on phase-locked loop (PLL) circuits, which can disrupt clock signals and prevent seamless mode switching during operations like cellular phone calls.
Innovation Solution
The apparatus and method involve a controller that manages 2^n phase signal generation stages with odd and even stages, using active periodic binary signals and steady-state signals to maintain deterministic phase relationships and consistent load on the PLL, allowing for seamless transitions between 2^n and 2^(n-1) phase modes without disturbing the PLL, using a frequency divider and clock generator to maintain load consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system transitions between different phase modes (e.g., eight-phase to four-phase), then the power consumption is reduced and distortion is minimized, but the phase shifts become indeterministic and the PLL load changes, disrupting clock signals
Solution Approach 1:
The patent applies preliminary action by pre-establishing deterministic phase relationships through careful design of the phase signal generation circuitry. The system pre-configures the phase shifters and signal paths to ensure that when mode transitions occur, the phase relationships remain predictable and deterministic, avoiding the indeterministic phase shifts that would normally disrupt operation during cellular phone calls
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the phase mode (number of phases) based on operating conditions. The system can switch between different phase configurations (e.g., eight-phase to four-phase) to optimize power consumption and reduce distortion, while maintaining deterministic phase relationships through controlled parameter transitions that preserve signal integrity
2Use of energy by moving object
If the system transitions between different phase modes, then power consumption is reduced, but the load on the PLL changes, causing clock signal disruption
Solution Approach 1:
The patent employs an intermediary approach by using carefully designed signal distribution circuitry and phase switchers that act as mediators between different phase modes. These intermediary components ensure smooth transitions by maintaining continuous, deterministic phase relationships during mode changes, preventing disruptions to the clock signal and enabling seamless operation during transitions
3Object-generated harmful factors
If the system uses 2^n phase signals, then signal quality and distortion reduction are improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the phase configuration adjustable and adaptive rather than fixed. The system can dynamically switch between different phase modes (e.g., four-phase, eight-phase, or other configurations) based on real-time operating conditions, allowing it to use higher phase counts when distortion reduction is critical and lower phase counts when power conservation is prioritized
Data Source
AI summary
The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ( )}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ( )}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ( )}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ( )}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ( )}(n−1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ( )}(n−1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ( )}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ( )}(n−1) odd stages or the 2{circumflex over ( )}(n−1) even stages to collectively generate a 2{circumflex over ( )}(n−1) phase signal in a second mode.