Injection-Locked PLL Startup Using Binary Search DCO Tuning
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Solution Overview
Problem
Conventional PLL circuits face challenges in achieving high-speed startup operations due to delays in frequency entrainment and phase locking, which are influenced by feedback control methods and fluctuate with environmental conditions.
Innovation Solution
An injection-locked PLL circuit is designed with a digitally controlled oscillator that oscillates based on a selection signal, using a binary search method to update the control code during startup, allowing for rapid phase locking without feedback delay, and includes a window generator to manage the injection edge and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback control method is used for frequency entrainment and phase locking, then the PLL circuit can achieve stable operation, but the startup time increases due to feedback delay
Solution Approach 1:
The patent applies preliminary action by performing feedforward frequency entrainment before feedback phase locking. The digitally controlled oscillator is first frequency-entrained to the reference clock using feedforward control, establishing a preliminary synchronized state. Subsequently, feedback phase locking is applied to achieve precise phase alignment. This two-stage approach reduces overall startup time by avoiding the need to wait for slow feedback convergence during the initial frequency acquisition phase.
Solution Approach 2:
The patent implements dynamics by switching between different control modes during startup. The system dynamically transitions from feedforward frequency entrainment mode to feedback phase locking mode. The control mechanism adapts its operation: initially using feedforward control for rapid frequency acquisition, then switching to feedback control for precise phase synchronization, thereby optimizing performance at different startup stages.
2Reliability
If conventional feedback control is used, then phase locking can be achieved, but the phase locking delay fluctuates with environmental conditions
Solution Approach 1:
The patent introduces feedforward frequency entrainment as an intermediary step between reference clock input and final phase locking. This intermediary mechanism performs preliminary frequency synchronization that is less sensitive to environmental variations. By establishing frequency alignment through the feedforward path before applying feedback phase locking, the system reduces the impact of environmental conditions on overall phase locking performance and minimizes delay fluctuations.
3Reliability
If analog PLL circuit architecture is used, then high reliability is achieved, but chip area increases due to loop filter requirements
Solution Approach 1:
The patent replaces the mechanical/analog loop filter component with a digital signal processing approach. Instead of using an analog low-pass filter that occupies significant chip area, the system employs digital filtering and signal processing techniques in the digitally controlled oscillator and feedback circuitry. This substitution maintains the reliability benefits of analog PLLs while achieving compact integration suitable for modern CMOS technology.
Solution Approach 2:
The patent changes the operational parameters and control methodology from purely analog to a hybrid digital-analog approach. The digitally controlled oscillator uses digital control codes to adjust oscillation frequency, replacing the need for large analog loop filters. The system transforms the control domain parameters, using digital frequency control words and phase detection algorithms to achieve the same reliability objectives with reduced hardware footprint.
Data Source
AI summary
A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.