Phase-Locked Loop Start-Up Control for Overshoot-Free Locking
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Solution Overview
Problem
Conventional phase-locked loops experience prolonged start-up periods due to frequency overshoots when increasing gain to achieve desired frequency and phase, leading to oscillations around the desired output frequency.
Innovation Solution
The phase-locked loop is divided into two stages during start-up: frequency tuning, where the desired output frequency is reached with a constant oscillator control signal, and phase tuning, where the phase evaluation block is enabled after detecting a subsequent clock edge, allowing variation of the control signal to achieve both desired frequency and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the gain of the control loop is increased to achieve faster frequency change, then the start-up period is shortened, but frequency overshoots occur causing oscillations around the desired frequency
Solution Approach 1:
The patent divides the phase-locked loop operation into two distinct stages: a frequency acquisition stage where the VCO frequency is rapidly tuned to the desired frequency, and a phase adjustment stage where the phase is fine-tuned while maintaining frequency stability. This segmentation allows the system to achieve fast frequency changes without causing harmful oscillations, as each stage has optimized control parameters for its specific function.
Solution Approach 2:
The patent implements dynamic switching between different control modes during operation. The control logic automatically transitions from open-loop frequency tuning to closed-loop phase control based on real-time frequency detection. This dynamic adaptation allows the system to optimize performance at different operational phases, achieving both fast start-up and stable frequency maintenance.
2Speed
If the gain of the control loop is increased to achieve faster frequency change, then the frequency tuning speed is improved, but frequency overshoots and oscillations occur
Solution Approach 1:
The patent separates frequency tuning and phase control into distinct operational stages. During the frequency acquisition stage, high gain is applied to achieve rapid frequency changes. Once the desired frequency is reached, the system transitions to the phase adjustment stage where gain is reduced or control is switched to maintain precise frequency accuracy. This segmentation allows high speed and high precision to coexist at different times in the operation cycle.
Solution Approach 2:
The patent implements preliminary frequency tuning before enabling full phase control. The frequency acquisition stage prepares the VCO by rapidly bringing it to the target frequency range, and only after this preliminary action is complete does the system enable precise phase-controlled adjustments. This preliminary action prevents overshoots by establishing the correct frequency baseline before fine control is applied.
3Reliability
If the phase evaluation block remains enabled during frequency tuning, then phase control is continuous, but frequency overshoots occur due to premature phase adjustments
Solution Approach 1:
The patent implements dynamic control of the phase evaluation block based on operational stage. During frequency acquisition, the phase evaluation block is disabled to prevent interference with rapid frequency tuning. Once frequency stability is achieved, the phase evaluation block is dynamically enabled to provide continuous phase control. This dynamic switching optimizes both speed and reliability by applying the right control mechanism at the right time.
Data Source
AI summary
A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.