PLL Startup Pre-Charging to Limit Overshoot and Lock Time
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Solution Overview
Problem
Phase-locked loops in digital systems experience lengthy startup times and significant frequency overshoot during initialization, leading to increased leakage currents and dynamic consumption due to the presence of feedback loops and capacitive networks.
Innovation Solution
A method involving a reference signal with a 50% duty cycle, resetting the divider at each rising signal edge, and applying a pre-charging current to a resistive capacitive filter during the startup phase to reduce startup time and frequency overshoot, with the charge pump circuit disconnected during this phase to minimize current constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional phase-locked loop with feedback loop and capacitive network is used, then the loop stability is improved, but the startup time becomes very lengthy (greater than 100 μs)
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitive filter through a dedicated pre-charging current source before the normal charge pump operation begins. This preliminary charging action reduces the initial voltage difference that would otherwise cause lengthy startup time, while the feedback loop and capacitive network remain in place to ensure loop stability during and after the pre-charging phase.
2Stability of the object's composition
If a conventional phase-locked loop is used, then the loop stability is improved, but frequency overshoot reaches up to 25% of the final nominal value
Solution Approach 1:
The pre-charging current source performs preliminary action by charging the capacitive filter to a voltage level closer to the target frequency before the charge pump begins normal operation. This reduces the voltage swing and prevents excessive frequency overshoot (limiting it to a few percent instead of 25%), while the feedback loop maintains loop stability throughout the process.
Solution Approach 2:
The patent changes the operating parameters of the capacitive filter by introducing a pre-charging current source that sets the initial voltage parameter of the filter capacitor. This parameter change (initial voltage level) directly controls the frequency overshoot behavior, reducing it from 25% to a few percent of the final nominal value, while the feedback loop ensures stability is maintained.
3Reliability
If the digital circuit of the PLL is designed to withstand higher frequency during startup, then the frequency overshoot tolerance is improved, but leakage currents and dynamic consumption increase
Solution Approach 1:
The pre-charging current source performs preliminary action by establishing the correct voltage level before full-power operation begins. This eliminates the need for the digital circuit to tolerate excessive frequency overshoot (25%), as the frequency now only overshoots by a few percent. Consequently, the circuit can be designed for normal operating conditions, significantly reducing leakage currents and dynamic consumption while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces startup time to around thirty microseconds and frequency overshoot to a few percent, making the phase-locked loop operation more efficient and less dependent on charge pump constraints.
Implementation Method 1
a resistive capacitive filter connected to the input of the oscillator
Implementation Method 2
applying a pre-charging current to a resistive capacitive filter
Data Source
AI summary
The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.