PLL Loop Filter State Restore for Faster Frequency Switching
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Solution Overview
Problem
Phase-lock loop (PLL) circuits experience significant delay when synchronizing to a clock signal with a frequency outside their current operating range, particularly in low-jitter clock generation systems, due to the need for reconfiguration and stabilization at the new frequency.
Innovation Solution
The PLL circuit includes a storage mechanism to store and restore the complete state of the loop filter, allowing for rapid switching between selectable frequency ranges, thereby reducing the lock time when changing frequency settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PLL re-configures to a new operating frequency outside the current range, then the PLL can synchronize to different frequency requirements, but the lock time increases significantly
Solution Approach 1:
The patent stores the state of the loop filter in advance before frequency switching occurs. When a frequency change is detected, the stored state is restored immediately, allowing the PLL to skip the lengthy stabilization process and achieve lock much faster than conventional reconfiguration methods
Solution Approach 2:
The patent creates a copy of the loop filter state at one frequency and stores it for later use. When switching to that frequency, the stored state copy is restored, eliminating the need to重新 establish the filter state from scratch and significantly reducing lock time
2Speed
If the loop filter bandwidth is increased temporarily to reduce acquisition time, then the synchronization speed improves, but the system introduces significant delay when returning to lower bandwidth operation
Solution Approach 1:
The patent dynamically switches between different loop filter states corresponding to different frequency ranges. Instead of permanently changing the bandwidth, the system selectively restores appropriate pre-stored states, achieving fast synchronization without the prolonged delay associated with bandwidth switching methods
Data Source
AI summary
A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.