PLL Stop Detection to Shorten Lock Time in Clock Control Circuits
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Solution Overview
Problem
In existing semiconductor integrated circuits, the lock time is prolonged due to the continued operation of the phase comparator, which causes the loop filter to charge or discharge, resulting in fluctuations in the control voltage input to the voltage-controlled oscillator, even when the base clock signal is stopped.
Innovation Solution
A semiconductor integrated circuit is designed with a phase comparator, a charge pump, a feedback unit, and a stop detection unit. The stop detection unit initializes the comparison result when the reference clock signal is stopped, thereby preventing further fluctuations in the control voltage and reducing the lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase comparator continues to output comparison results while the base clock signal is stopped, then the loop filter is charged or discharged causing control voltage fluctuations, but the lock time becomes longer as the stop period is longer
Solution Approach 1:
The stop detection unit detects the stop of the base clock signal in advance and initializes the comparison result before the clock signal resumes. This preliminary action prevents the loop filter from charging or discharging during the stop period, avoiding control voltage fluctuations and enabling faster lock time when the clock signal resumes.
2Use of energy by moving object
If the voltage-controlled oscillator is stopped while the base clock signal is stopped, then power consumption is reduced, but the control voltage fluctuates and lock time is prolonged
Solution Approach 1:
The invention extracts the stop detection and comparison result initialization function from the main PLL circuit. By adding a separate stop detection unit that independently monitors the base clock signal and initializes the phase comparator output, the system can stop the VCO for power savings without allowing the phase comparator to generate erroneous comparison results during the stop period.
Data Source
AI summary
In a circuit provided with a phase comparator, a lock time is shortened.The phase comparator compares between a phase of a reference clock signal that has been input and a phase of a feedback clock signal, and outputs a comparison result. A charge pump generates a control voltage for control of a frequency of the feedback clock signal on the basis of the comparison result. A feedback unit generates the feedback clock signal in response to the control voltage. A stop detection unit detects whether or not the reference clock signal is stopped, and initializes the comparison result in a case where the reference clock signal is stopped.