PLL Loop Filter Using Switched Resistance for Low-Noise Compact Design
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low silicon area and low power consumption, particularly due to large capacitor requirements in analog PLLs and high 1/f noise, while digital PLLs struggle with power efficiency, especially in older CMOS processes.
Innovation Solution
The implementation of a switched resistor network in the PLL loop filter, which adjusts effective resistance based on pulsing properties of a control signal, reducing 1/f noise and capacitor area, and incorporating high gain phase detectors and frequency detection methods using switched capacitors for rapid frequency acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large capacitor is used in the loop filter of an analog PLL, then the PLL can achieve low phase noise and stable operation, but the silicon area increases significantly
Solution Approach 1:
The patent changes the resistance parameter dynamically using a switched resistor network controlled by a modulator. By varying the resistance value based on a dither signal, the system achieves an effective lower resistance than physically implementable, thereby reducing the required capacitor size while maintaining the same time constant and noise performance.
Solution Approach 2:
The patent introduces dynamic switching of resistor elements in the loop filter. The switched resistor network changes its configuration based on a modulating signal, creating a time-varying resistance that effectively reduces the RC time constant and allows for smaller capacitor values without compromising stability or noise performance.
2Speed
If continuous switching signals are used in a digital PLL, then frequency control is achieved, but power consumption increases
Solution Approach 1:
The patent uses periodic switching of the resistor network at a specific frequency (e.g., twice the reference frequency) rather than continuous switching. This periodic action achieves the same frequency control function while allowing the circuit to remain in a low-power state during non-switching intervals, significantly reducing average power consumption.
Solution Approach 2:
The patent preemptively reduces power consumption by using a switched resistor network that only activates when needed for frequency adjustment. The modulator circuit prepares the resistance changes in advance based on predicted frequency requirements, avoiding continuous high-power operation while maintaining responsive frequency control.
3Area of stationary object
If a switched resistor network is used to reduce capacitor size, then silicon area decreases, but 1/f noise may increase
Solution Approach 1:
The patent maintains continuous useful action in the loop filter by ensuring the switched resistor network operates continuously at a high frequency. This continuous switching creates an effective resistance that is smooth and stable, avoiding the discontinuities that would generate 1/f noise, while still allowing for reduced capacitor size.
Solution Approach 2:
The patent carefully controls the parameters of the switched resistor network, including switching frequency and duty cycle, to optimize the trade-off between area reduction and noise performance. By selecting appropriate switching frequencies well above the signal bandwidth and using proper modulation schemes, the system achieves area reduction without significant 1/f noise generation.
Data Source
AI summary
Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.