Switched-Resistor PLL Loop Filter for Low-Area, Low-Noise Locking
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low silicon area and low power consumption, particularly due to large capacitor requirements in analog PLLs and high 1/f noise, while digital PLLs struggle with power efficiency, especially in older CMOS processes.
Innovation Solution
The implementation of a switched resistor network in PLL circuitry, which adjusts effective resistance based on pulsing properties of a control signal, reducing the need for large capacitors and minimizing 1/f noise, combined with high gain phase detectors and efficient frequency detection methods using switched capacitors for rapid frequency acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge pump PLL with RC network is used, then phase locked loop functionality is achieved, but large capacitor area is required
Solution Approach 1:
The patent transforms the continuous RC filter into a switched-capacitor filter by changing the operational parameters. Capacitors are switched between different states (charging, discharging, holding) to dynamically implement filtering functionality, reducing the required capacitor area while maintaining PLL performance.
Solution Approach 2:
The switched capacitor network operates periodically, with capacitors being charged and discharged in rhythmic cycles controlled by clock signals. This periodic switching action replaces the continuous operation of traditional RC filters, enabling area reduction while preserving the necessary filtering characteristics.
2Reliability
If a charge pump PLL is used, then phase locked loop functionality is achieved, but 1/f noise is significant
Solution Approach 1:
The patent replaces the charge pump mechanism (which generates significant 1/f noise) with a current-mode switched capacitor network. This substitution eliminates the noisy charge pumping action while maintaining the necessary current control functionality for phase detection and loop filtering.
Solution Approach 2:
The switched capacitor network acts as an intermediary between the phase detector and voltage-controlled oscillator, providing noise-free current control. The switching action occurs at higher frequencies where noise is less problematic, and the capacitive coupling filters out low-frequency noise components.
3Measurement precision
If a digital PLL with many switching signals is used, then frequency detection capability is improved, but power consumption increases
Solution Approach 1:
The patent divides the PLL into distinct functional blocks: a digital phase detector for precise frequency/phase measurement, and a switched capacitor filter for noise-free signal conditioning. Each segment performs its specific function efficiently, avoiding the power overhead of fully digital implementations while maintaining detection precision.
Solution Approach 2:
The patent employs dynamic switching of capacitor connections based on the detection state. During frequency acquisition, the switched capacitor network adapts its configuration to optimize detection speed, then transitions to a lower-power holding mode during steady-state operation, reducing overall power consumption while maintaining detection capability.
Data Source
AI summary
Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry. The frequency detection circuitry includes (i) circuitry to generate a signal which is representative of the frequency of the output signal of the phase-locked loop circuitry, (ii) comparison circuitry to compare the signal which is representative of the frequency of the output signal of the phase-locked loop circuitry to a reference input to the phase-locked loop circuitry, and (iii) a switched capacitor network including at least one capacitor.