PLL Signal Synchronization Circuit With Half-Period Setup Timing
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Solution Overview
Problem
Conventional signal synchronization circuits face challenges in quantitatively accounting for manufacturing variations between different clock synchronization systems, leading to potential anomalies during device inspection in mass production.
Innovation Solution
A semiconductor device with a signal synchronization circuit that includes a phase-locked loop (PLL) circuit and flip-flops, where the setup time for synchronization is set to half the period of the reference clock signal, allowing for efficient signal conversion between differing clock systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay element is interposed between flip-flops of one system and flip-flops of another system to ensure setup time and hold time, then signal synchronization between different clock systems is achieved, but manufacturing variation cannot be quantitatively controlled and device inspection anomalies occur in mass production
Solution Approach 1:
The invention changes the setup time parameter from a fixed value to one that is dynamically determined based on the relationship between clock frequencies. Specifically, the setup time is set to one half of the period of the reference clock signal divided by the frequency division ratio, allowing the synchronization circuit to adapt to different manufacturing variations while maintaining reliable operation across mass production.
2Adaptability or versatility
If conventional signal synchronization circuit configuration is used, then signal transfer between different clock systems is enabled, but operational tolerance decreases due to unquantified manufacturing variations
Solution Approach 1:
The invention introduces a feedback mechanism where the setup time is determined based on the reference clock signal period and frequency division ratio. This feedback approach ensures that the synchronization circuit maintains appropriate timing margins regardless of manufacturing variations, thereby preserving operational tolerance while enabling signal transfer between different clock systems.
3Ease of operation
If flip-flops controlled by different clock signals are used for signal synchronization, then clock signal conversion is achieved, but quantitative control of setup time and hold time becomes difficult
Solution Approach 1:
The invention provides a clear quantitative definition for setup time based on the reference clock period and frequency division ratio. By setting the setup time to one half of the reference clock period divided by the division ratio, the design achieves both ease of operation for signal synchronization and precise measurement/control of the setup time parameter.
Data Source
AI summary
A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.