Multi-Frequency PLL Synchronization for Low-Noise Multi-Carrier LO

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Solution Overview

Problem

Modern wireless communication networks face challenges in managing multiple carriers and Local Oscillator (LO) signals at different frequencies due to high phase noise, frequency pulling, and power consumption issues, particularly in wideband converters and multi-Phase Locked Loop (PLL) designs.

Innovation Solution

A multi-carrier transceiver architecture with integer-N PLLs operating on the same reference frequency but with different division numbers, synchronized by a PLL synchronization circuit to generate LO signals at different frequencies, reducing phase noise and mitigating frequency pulling through RF filters and oscillator isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple PLL circuits operate independently at different frequencies, then frequency flexibility is improved, but phase noise increases and coupling problems occur

Engineering Contradiction:
Improvefrequency flexibilityVSAvoidphase noise
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent merges multiple independent PLL circuits into a synchronized system where all PLLs share a common reference frequency and are phase-locked together. This combining approach maintains frequency flexibility through different division ratios while reducing phase noise by eliminating independent oscillator coupling and spurious signals.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The synchronized PLL system provides multi-functionality by generating multiple LO frequencies from a single reference source. The system can simultaneously support different carrier frequencies (e.g., 7-15 GHz range) while maintaining phase coherence, thus one system serves multiple frequency conversion purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If wideband converters process entire frequency range, then single clock frequency is achieved, but power consumption increases substantially

Engineering Contradiction:
Improveconverter architectureVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent segments the wideband frequency processing into multiple narrowband converter stages, each handling a specific frequency range. Each segment uses its own PLL and mixer to convert to baseband, allowing optimized power consumption for each narrowband processor while collectively covering the entire 7-15 GHz range.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If narrow-band converters process only carrier signals, then power consumption is reduced, but multiple PLLs with different frequencies are required

Engineering Contradiction:
Improvepower consumptionVSAvoidPLL system
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent combines multiple narrowband PLL circuits into a synchronized system sharing a common reference frequency. This merging reduces device complexity by eliminating independent frequency sources and their associated coupling problems, while still enabling multiple frequency conversions through different division ratios in each PLL.

Inventive Principle:
Principle #5Merging (Combining)

4Adaptability or versatility

If oscillators operate at different frequencies, then multiple carriers can be processed, but frequency pulling and spurious signals occur

Engineering Contradiction:
Improvemulti-carrier processingVSAvoidfrequency pulling
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent merges multiple oscillators into a synchronized system where all oscillators are phase-locked to a common reference frequency. This combining eliminates frequency pulling and spurious signals by ensuring all oscillators operate coherently, while still generating different LO frequencies through integer division ratios for processing multiple carriers.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach achieves low phase noise and efficient processing of multiple carriers with reduced power consumption and chip area, enabling flexible frequency grid generation and improved performance in beamforming and MIMO techniques.

Implementation Method 1

A multi-carrier transceiver architecture with integer-N PLLs operating on the same reference frequency but with different division numbers, synchronized by a PLL synchronization circuit to generate LO signals at different frequencies

Methodology Applied
Scientific EffectPhase Locked Loop:

Data Source

PatentUS20240275392A1Multi-Carrier Transceiver and Multi-Frequency PLL System
Publication Date: 2024.08.15 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US20240275392A1 patent drawing
  • US20240275392A1 patent drawing
  • US20240275392A1 patent drawing

AI summary

A multi-carrier transceiver receives and transmits wireless communication signals on multiple carriers simultaneously. To generate Local Oscillator (LO) signals for mixers operating at different frequencies, a multi-frequency LO signal generating circuit includes a set of integer-N Phase Locked Loop (PLL) circuits. All PLL circuits receive the same reference frequency, but output different frequency LO signals, each at an integer multiple of the reference frequency. The LO signal frequencies are thus on an equidistant frequency grid having a granularity of the reference frequency. Spurs are also at multiples of the reference frequency, and can be easily filtered. A fractional-N PLL circuit may generate the reference frequency, making the frequency grid adjustable. A plurality of the PLL circuits in the set output a phase error feedback signal to a phase error correction circuit, and receive a phase error control signal that phase-locks the plurality of PLL circuits together and mitigates phase noise deviations between them. PLL circuits operating near a transmitter frequency are not in the phase-locked plurality, so all PLL circuits are not frequency pulled. Complex channel select filters are used for carriers not aligned with a LO signal.