PLL Synthesizer Digital Reference for Low Phase Noise

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Solution Overview

Problem

Current frequency synthesizers for RF transceivers face challenges in achieving high reference frequencies with fine frequency resolution while maintaining low in-band phase noise, as fractional-N synthesizers suffer from elevated phase noise due to non-linearities and integer-N synthesizers experience high reference spurs leading to slow settling times.

Innovation Solution

A frequency synthesizer design that incorporates a digital processor to generate a high-reference frequency with fine-tuning capabilities, using a digital-to-analog converter and phase locked loop to produce a filtered analog reference signal, allowing for integer-N phase locked loop operation with fine frequency resolution and low in-band phase noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If fractional-N synthesizer is used to achieve high reference frequency with fine frequency resolution, then frequency resolution is improved, but in-band phase noise increases due to non-linearities

Engineering Contradiction:
Improvefrequency resolutionVSAvoidin-band phase noise
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a digital processor as an intermediary component that generates the reference signal digitally with high precision, converts it to analog via DAC, and filters it before input to the PLL. This intermediary digital processing stage enables fine frequency resolution without the non-linearities that cause phase noise in traditional fractional-N synthesizers.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the traditional analog fractional-N frequency synthesis mechanism with a digital processing approach. The digital processor generates the reference signal, and the DAC converts it to analog, eliminating the non-linear mechanical/electrical switching operations that cause phase noise while preserving fine frequency resolution.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Object-generated harmful factors

If integer-N synthesizer is used to reduce in-band phase noise, then phase noise is improved, but reference spurs increase causing slow settling time

Engineering Contradiction:
Improvein-band phase noiseVSAvoidsettling time
Core Design Contradiction:
Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The patent changes the reference signal parameters by generating it digitally at a high frequency (e.g., 40 MHz or higher) with fine tunability, rather than using a fixed low-frequency crystal reference. This parameter change allows the system to achieve fast settling times while maintaining low phase noise through the integer-N PLL architecture.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If high reference frequency is used to reduce reference spurs and improve settling time, then settling time is improved, but achieving fine frequency resolution becomes more difficult

Engineering Contradiction:
Improvesettling timeVSAvoidfrequency resolution
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent implements a dynamic digital reference signal generation system where the frequency can be precisely adjusted in real-time. The digital processor dynamically generates reference signals with fine frequency resolution, and the DAC converts these dynamic adjustments to analog domain, enabling both fast settling and fine resolution simultaneously.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the generation of high-reference frequencies with fine frequency resolution and low in-band phase noise, addressing the limitations of both fractional-N and integer-N synthesizers by combining their advantages without introducing their drawbacks.

Implementation Method 1

A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal

Methodology Applied
Scientific EffectDigital-to-Analog Conversion:

Implementation Method 2

a low pass filter filters the analog reference signal to produce a filtered analog reference signal

Methodology Applied
Scientific EffectFiltering: Filter (electronic)

Implementation Method 3

a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal

Methodology Applied
Scientific EffectPhase Locked Loop Frequency Synthesis:

Data Source

PatentUS7324789B2PLL frequency synthesizer architecture for low phase noise and reference spurs
Publication Date: 2008.01.29 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7324789B2 patent drawing
  • US7324789B2 patent drawing
  • US7324789B2 patent drawing

AI summary

A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.