PLL Reference Switching Using TDC Averaging and Phase Offset Hold
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Solution Overview
Problem
Phase-locked loops (PLLs) experience sudden frequency and phase shifts when switching between reference clocks, disrupting operations, especially in communication transceivers where packet corruption or dropout can occur.
Innovation Solution
Incorporating a multiplexer with multiple reference clock inputs, an averager circuit, and a digital loop filter that temporarily freezes frequency control when switching reference clocks, averaging new TDC output values, and subtracting the average from subsequent values to maintain a stable output clock frequency and phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PLL switches between different reference clocks, then the PLL can adapt to different frequency requirements, but sudden frequency and phase shifts occur disrupting operations
Solution Approach 1:
The system performs preliminary actions by freezing the digital loop filter before switching reference clocks, and by pre-calculating the phase offset using the averager circuit. This prepares the system in advance to prevent frequency and phase shifts when the actual switch occurs, thereby maintaining operation continuity while enabling reference clock adaptability.
Solution Approach 2:
The averager circuit acts as an intermediary between the TDC and the digital loop filter. It computes the average of TDC output values to determine a phase offset, which is then used to adjust subsequent TDC outputs. This intermediary processing smooths the transition between reference clocks, preventing sudden frequency and phase shifts while maintaining the ability to switch between different reference clocks.
2Stability of the object's composition
If the PLL maintains phase lock with a single reference clock, then frequency and phase stability is achieved, but the system cannot adapt to different frequency requirements
Solution Approach 1:
Before switching to a new reference clock, the system freezes the digital loop filter and uses the averager circuit to pre-calculate the phase offset. This preliminary action ensures that when the reference clock switch occurs, the system can immediately maintain frequency and phase stability while adapting to the new clock, thus achieving both stability and adaptability.
Solution Approach 2:
The system changes parameters by adjusting the TDC output using a calculated phase offset when switching reference clocks. The averager circuit computes the average of TDC outputs to determine this offset, which is then applied to maintain the PLL's frequency and phase relationship with the new reference clock, enabling adaptability without sacrificing stability.
3Device complexity
If the PLL uses a simple reference clock switch, then device complexity is minimized, but packet corruption or dropout occurs during switching
Solution Approach 1:
The averager circuit serves as an intermediary that processes TDC output values to calculate a phase offset during reference clock switching. This adds minimal complexity to the switching mechanism while preventing packet corruption or dropout by ensuring smooth transitions that maintain frequency and phase stability, thus protecting packet transmission integrity.
Solution Approach 2:
The system performs preliminary calculations of the phase offset using the averager circuit before the actual reference clock switch occurs. This preliminary action prevents packet corruption during switching without requiring complex switching mechanisms, as the phase offset preparation is done in advance using simple averaging operations.
Data Source
AI summary
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.