Digital PLL TDC Calibration Using Error Lookup Correction

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Solution Overview

Problem

Current digital Phase Locked Loops (PLLs) face challenges in achieving low phase noise with limited power consumption and chip area, particularly due to the high power consumption of Time to Digital Converters (TDCs) and the difficulty in realizing high linearity and low noise with long delay lines, which affects the performance in fractional-N mode.

Innovation Solution

An improved calibration technique for TDCs in digital PLLs, involving a calibration unit that processes output data samples to generate a calibration lookup table by calculating error values and averaging them for each TDC output level, allowing for open-loop calibration without the need for de-wrapping, thus reducing power consumption and increasing calibration speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a long delay line is used to achieve high timing resolution (less than one inverter delay), then phase noise performance is improved, but power consumption and chip area increase substantially

Engineering Contradiction:
Improvetiming resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The delay line is divided into multiple identical delay cells (e.g., 64 cells) where each cell contributes a small, equal portion to the total delay. This segmentation allows the system to achieve long total delay (for high resolution) while keeping each individual cell simple and low-power. The TDC uses these segmented cells to measure time intervals by counting how many cells are traversed, achieving sub-inverter-delay resolution through the cumulative effect of many small segments.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If a long delay line is used to achieve high timing resolution, then phase noise performance is improved, but chip area increases substantially

Engineering Contradiction:
Improvetiming resolutionVSAvoidchip area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The delay line is divided into multiple identical delay cells (e.g., 64 cells) where each cell contributes a small, equal portion to the total delay. This segmentation allows the system to achieve long total delay (for high resolution) while keeping each individual cell simple and low-power. The TDC uses these segmented cells to measure time intervals by counting how many cells are traversed, achieving sub-inverter-delay resolution through the cumulative effect of many small segments.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If fractional-N mode is used to generate non-integer output frequencies, then frequency flexibility is improved, but linearity requirements increase due to fractional spurs

Engineering Contradiction:
Improvefrequency flexibilityVSAvoidlinearity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system employs a feedback mechanism where the TDC measures the actual phase difference between the reference signal and the divided feedback signal, and this measurement is used to generate a correction signal that compensates for fractional spurs. The TDC output controls a digital filter or correction mechanism that adjusts the TDC's own operation or the PLL's control signal, creating a feedback loop that actively cancels the non-linear effects and fractional spurs, enabling high-frequency flexibility with maintained linearity.

Inventive Principle:
Principle #23Feedback

4Measurement precision

If closed-loop TDC calibration is used to improve linearity, then measurement precision is improved, but calibration time increases

Engineering Contradiction:
ImprovelinearityVSAvoidcalibration time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs TDC calibration in advance, before normal PLL operation begins. During this preliminary calibration phase, the TDC is tested across its full range of operation points, and the measured errors are stored in a lookup table. During normal operation, the system simply queries this pre-computed lookup table rather than performing complex real-time calibration, thus achieving high linearity correction with minimal time penalty during actual operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12143116B2Time to digital converter calibration
Publication Date: 2024.11.12 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US12143116B2 patent drawing
  • US12143116B2 patent drawing
  • US12143116B2 patent drawing

AI summary

A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and reference signals. The calibration unit receives and processes data samples output from the TDC and generates a calibration lookup table in which each TDC output value has a calibration value. The calibration lookup table may be used for post-distortion. For each TDC output level the corresponding calibration value from the lookup table may be added to the output of the TDC for correction.