Multi-Phase PLL TDC Switching for Low-Power Fractional Phase Sensing
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Solution Overview
Problem
Managing power consumption and area associated with phase locked loops (PLLs) and time-to-digital converters (TDCs) becomes challenging as technology advances, particularly due to the need for efficient management of multiple phases and clock signals.
Innovation Solution
A multi-phase time-to-digital converter (TDC) is integrated into the PLL, featuring a first phase finder, phase predictor, second phase finder, and phase switch, which generate fractional phase signals based on reference frequencies and clock signals, allowing for reduced power consumption by toggling components on and off based on phase errors and covering portions of the clock period with fewer inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-phase TDC is used to generate fractional phase signals for all phases continuously, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by enabling the multi-phase TDC to operate only during specific intervals when phase measurement is required, rather than continuously. The TDC is activated during phase acquisition and tracking periods, and deactivated during stable operation phases, thereby reducing overall power consumption while maintaining measurement precision when needed.
Solution Approach 2:
The patent applies dynamics by making the TDC operational state variable - switching between active and inactive states based on PLL operational requirements. The system dynamically adjusts TDC operation mode (continuous vs. periodic) based on phase locking status and measurement needs, optimizing the balance between precision and power consumption.
2Measurement precision
If multiple phase finders are used to cover different phase ranges, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the phase measurement range into multiple segments, each handled by a dedicated phase finder. The first phase finder measures phase in a first range, the second phase finder measures phase in a second range, and the phase predictor predicts phase for a third range. This segmentation enables precise measurement across the entire phase spectrum while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent implements multi-functionality by designing the multi-phase TDC to perform multiple functions: the first phase finder for initial phase acquisition, the second phase finder for refined measurement, and the phase predictor for forward phase estimation. A single integrated TDC structure handles diverse measurement scenarios, reducing overall system complexity compared to separate dedicated circuits for each function.
3Area of stationary object
If the number of inverters is reduced to decrease area, then area requirement is reduced, but measurement precision may deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the phase measurement task across multiple specialized components (first phase finder, second phase finder, phase predictor) rather than using a single large-scale inverter-based TDC. Each segment uses a limited number of inverters optimized for its specific function, collectively achieving high precision while minimizing total inverter count and area.
Solution Approach 2:
The patent replaces traditional mechanical inverter-based phase measurement mechanisms with a hybrid approach combining digital logic (phase predictor using FCW and PHR signals) and selective analog/digital phase finding circuits. This substitution reduces reliance on extensive inverter chains, thereby reducing area while maintaining or improving precision through intelligent signal processing.
Data Source
AI summary
One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.