PLL TDC Sub-Range Control for Sub-0.3 ps Linear Resolution
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Solution Overview
Problem
Conventional time-to-digital converter (TDC) circuits face challenges in achieving resolutions below 0.3 picoseconds and encounter integral nonlinearity issues due to phase detectors, which hinder their performance in high-speed systems.
Innovation Solution
A phase-locked loop (PLL) circuit comprising a TDC, loop filter, digital controlled oscillator (DCO), sigma-delta modulator (SDM), and prediction circuit, along with a sub-range controlling circuit using capacitor banks and control logic, dynamically adjusts voltage levels to mitigate nonlinearity and achieve high resolution, incorporating a prediction method to compensate for voltage folding and quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional TDC circuits are used to achieve high resolution, then measurement precision is improved, but integral nonlinearity problems occur due to phase detector limitations
Solution Approach 1:
The patent introduces a voltage folding circuit as an intermediary component between the phase detector and ADC. This circuit folds the voltage output from the phase detector to keep it within the linear input range of the ADC, thereby eliminating integral nonlinearity while preserving high measurement precision. The folding circuit acts as a mediator that transforms the phase detector's voltage output into a form suitable for accurate ADC conversion.
Solution Approach 2:
The patent applies preliminary action by predicting the voltage output from the phase detector before it reaches the ADC. The prediction circuit calculates the expected voltage level and adjusts the folding operation in advance to ensure the voltage remains within the ADC's linear range. This proactive approach prevents integral nonlinearity from occurring in the first place.
2Productivity
If conventional TDC circuits operate at high speed, then productivity is improved, but time resolution deteriorates below 0.3 picoseconds
Solution Approach 1:
The patent implements dynamics by making the voltage folding operation adaptive and controllable. The folding circuit is dynamically adjusted based on the predicted voltage levels and operational requirements, allowing the system to optimize between speed and resolution. The controllable folding mechanism enables the system to maintain high-speed operation while preserving sub-0.3 picosecond time resolution through dynamic range management.
3Measurement precision
If voltage level is limited in voltage range to generate specific digital output, then measurement precision is improved, but device complexity increases with prediction circuit and sub-range controlling circuit
Solution Approach 1:
The patent applies segmentation by dividing the voltage range into multiple sub-ranges using capacitor banks. Each capacitor bank segment handles a specific voltage portion, and the control logic selectively activates appropriate segments. This segmentation approach improves measurement precision by ensuring each segment operates within its optimal range while keeping individual segment complexity manageable through modular design.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting capacitor bank configurations to alter voltage folding ratios. By changing the effective capacitance values and connections based on predicted voltage levels, the system optimizes measurement precision for different operating conditions without requiring a completely different circuit architecture for each scenario.
Data Source
AI summary
A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.