Global PLL Timing Recovery with Delay Compensation Across Channels
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Solution Overview
Problem
Loop delay in timing control loops of phase-locked loops (PLLs) degrades system performance, particularly in data storage applications, and existing delay compensation methods assume a constant frequency offset, limiting their effectiveness in tracking rapid frequency variations.
Innovation Solution
A global PLL circuit with a delay compensation circuit that applies correction terms based on current phase and frequency estimates, allowing for accurate tracking of frequency variations without assuming a specific frequency offset model, and is compatible with both single-channel and multi-track applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If delay compensation is implemented using a constant frequency offset model, then the PLL phase margin is improved, but the tracking capability degrades when rapid frequency variations occur
Solution Approach 1:
The patent transitions from a static constant frequency offset model to a dynamic model that adapts to rapid frequency variations. The delay compensation circuit now uses a time-varying frequency offset model that can track and respond to changing frequency conditions, allowing the system to maintain both stability and adaptability under varying operational conditions.
Solution Approach 2:
The patent changes the parameter representation from a constant frequency offset to a time-varying frequency offset model. By allowing the frequency offset parameter to change dynamically based on observed signal characteristics, the system can adapt to rapid frequency variations while maintaining adequate phase margin through appropriate parameter selection.
2Device complexity
If implementation constraints are accepted, then the device complexity is reduced, but loop delay increases degrading PLL performance
Solution Approach 1:
The patent introduces a delay compensation circuit that performs preliminary correction of the phase error signal before it enters the main PLL loop. By compensating for the loop delay in advance, the system can use simpler implementation constraints without suffering from the negative effects of loop delay, thus maintaining PLL performance while accepting practical implementation limitations.
3Loss of time
If a prediction element is added to the PLL design, then delay compensation is achieved, but the system becomes limited to single channel applications
Solution Approach 1:
The patent designs a delay compensation circuit with a universal architecture that can function across multiple channels simultaneously. The circuit uses a multi-channel frequency offset estimator that processes signals from multiple channels and generates appropriate compensation signals for each, making the system adaptable to both single-channel and multi-track applications without requiring separate compensation circuits.
Data Source
AI summary
A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.