Fractional-N PLL Timing Adjustment for Modulation Noise Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional-N phase lock loops experience noise due to modulation of the division factor, which existing methods attempt to mitigate through high power consumption or complex circuitry, including the use of digital-to-analog converters that introduce thermal noise and nonlinearity.
Innovation Solution
A digitally controlled timing adjustment circuit is employed to correct pre-known timing errors, using a gain calibrated in a closed-loop manner to cancel noise, comprising a fixed-delay and variable-delay circuit with a tunable inverter and variable capacitor, and a self-calibrating digital phase detector to adjust the gain control signal based on noise cancellation and timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a digital-to-analog converter is used to cancel additive noise from division factor modulation, then noise cancellation is achieved, but thermal noise increases and power consumption rises
Solution Approach 1:
The patent extracts and separates the noise cancellation function from the traditional digital-to-analog converter approach. By using a dedicated noise cancellation signal path that directly adjusts the VCO control voltage based on the modulation-induced noise characteristics, the system cancels additive noise without requiring high-power DAC operation, thus resolving the contradiction between noise cancellation and power consumption
Solution Approach 2:
The patent introduces an intermediary noise cancellation mechanism that operates in the voltage domain rather than directly converting digital noise signals. The noise cancellation signal serves as an intermediary that compensates for the additive noise by adjusting the VCO control voltage, avoiding the thermal noise generation inherent in high-power DAC operation
2Object-affected harmful factors
If a digital-to-analog converter is used to cancel additive noise from division factor modulation, then noise cancellation is achieved, but circuit complexity increases due to nonlinearity compensation requirements
Solution Approach 1:
The patent extracts the noise cancellation function from the complex DAC-based approach and implements it through a simplified voltage adjustment mechanism. By directly manipulating the VCO control voltage with a noise cancellation signal, the system eliminates additive noise without requiring complex nonlinearity compensation circuits, thus resolving the contradiction between noise cancellation and circuit complexity
Solution Approach 2:
The patent uses a simplified model of the noise generation mechanism to create a noise cancellation signal that mirrors the additive noise characteristics. This copying approach allows the system to counteract the noise from division factor modulation using a simple voltage adjustment rather than complex circuitry, resolving the contradiction between effective noise cancellation and circuit complexity
3Device complexity
If a fixed division factor is used in the clock divider circuit, then circuit simplicity is maintained, but frequency tracking precision deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of the division factor through modulation, allowing the clock divider circuit to transition from a static fixed division factor to a dynamic variable division factor. This enables precise frequency tracking while maintaining relatively simple circuitry by using modulation techniques rather than complex programmable dividers, resolving the contradiction between circuit simplicity and frequency tracking precision
Solution Approach 2:
The patent changes the division factor parameter dynamically through modulation to achieve precise frequency tracking. By modulating the division factor between integer values, the system achieves non-integer average division ratios for precise frequency synthesis while maintaining simple integer-based divider circuits, resolving the contradiction between circuit simplicity and frequency tracking precision
4Adaptability or versatility
If the division factor is modulated to achieve fractional-N operation, then frequency synthesis flexibility is improved, but instantaneous noise increases
Solution Approach 1:
The patent converts the harmful instantaneous noise generated by division factor modulation into a predictable and cancelable signal. By analyzing the noise generation mechanism and creating a corresponding noise cancellation signal, the system transforms the harmful effect of modulation-induced noise into a benefit where the noise can be systematically compensated, resolving the contradiction between frequency synthesis flexibility and instantaneous noise
Solution Approach 2:
The patent implements a feedback mechanism where the noise cancellation signal is generated based on the known characteristics of the modulation-induced noise. This feedback approach allows the system to continuously compensate for instantaneous noise while maintaining flexible frequency synthesis through division factor modulation, resolving the contradiction between frequency synthesis flexibility and instantaneous noise
Data Source
AI summary
An apparatus having a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal, an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal, a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal, a controllable oscillator configured to receive the oscillator control signal and output a fifth clock, a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor, a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor, a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero, and a correlation circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.