PLL Timing Pulse Generation for Precise Optical Measurement
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Solution Overview
Problem
Existing optical measurement systems face challenges in generating precise and programmable timing pulses for photodetectors, particularly in turbid media like the brain, due to issues with clock mismatch and skew, which affect the accuracy of neural activity detection.
Innovation Solution
The implementation of Phase Lock Loop (PLL) circuit-based signal generation architectures, which provide robust and accurate timestamp signal buses, minimizing jitter and circuit complexity, and allowing for precise temporal positioning of timing pulses, thereby enhancing the precision of optical measurement systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional analog signal generation circuits are used, then circuit complexity is reduced, but timing precision and stability deteriorate due to temperature and voltage variations
Solution Approach 1:
The patent replaces traditional analog signal generation circuits with a Phase Lock Loop (PLL) circuit-based architecture. The PLL circuit uses digital signal processing and feedback control mechanisms to generate timing pulses, substituting analog components with a more precise digital system that is less sensitive to temperature and voltage variations.
Solution Approach 2:
The PLL circuit inherently employs feedback control to lock onto a reference frequency and maintain precise timing. The feedback mechanism continuously adjusts the phase and frequency of the generated signals to match the reference, ensuring high timing precision and stability despite environmental variations.
2Measurement precision
If PLL circuit-based signal generation is implemented, then timing precision is improved, but device complexity increases
Solution Approach 1:
The PLL circuit is designed to serve multiple functions within the optical measurement system, including generating timing pulses for photodetectors, providing clock signals for data acquisition, and synchronizing various system components. This multi-functionality reduces the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent integrates the PLL circuit-based signal generation architecture to simultaneously provide timing pulses, clock signals, and synchronization references for multiple system components. By merging these functions into a single unified architecture, the overall system complexity is managed more effectively.
3Measurement precision
If precise timing pulses are generated for photodetectors, then neural activity detection accuracy is improved, but the system becomes more sensitive to clock mismatch and skew
Solution Approach 1:
The PLL circuit uses feedback control to continuously monitor and adjust the phase and frequency of generated timing pulses against a reference clock. This feedback mechanism compensates for clock mismatch and skew, maintaining synchronization and reducing sensitivity to clock variations.
Solution Approach 2:
The PLL circuit dynamically adjusts its operation to adapt to changing conditions. The phase detector and frequency synthesizer continuously modify the timing pulse generation to maintain precision despite variations in clock signals, making the system more robust to dynamic changes.
Data Source
AI summary
An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.